Synchronous wired-or ACK status for memory with variable write latency

Patent metadata

Field	Value
Publication number	US-11973153-B2
Application number	US-202117445371-A
Country	US
Kind code	B2
Filing date	Aug 18, 2021
Priority date	Aug 7, 2012
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

First claim

What is claimed is:

1. A memory controller comprising:
a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller;
an acknowledgement interface to receive a combined acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, wherein the combined acknowledgment status packet is formed from a logical combination of individual acknowledgment status packets corresponding to each of the plurality of memory devices, wherein each of the individual acknowledgment status packets comprises a plurality of fields, wherein each of the individual acknowledgement status packets comprises acknowledgment information associated with a corresponding memory device of the plurality of memory devices and stored in a respective designated field of the plurality of fields, and wherein a remainder of the plurality of fields in each individual acknowledgment status packet besides the respective designated field comprise default values, the acknowledgment information to indicate whether the command was successfully received by the corresponding memory device; and
a memory controller core to decode the combined acknowledgment status packet to identify the acknowledgement information corresponding to each of the plurality of memory devices.

2. The memory controller of claim 1 , wherein each of the individual acknowledgment status packets comprises one field comprising acknowledgment information associated with the corresponding memory device and a plurality of fields comprising default values.

3. The memory controller of claim 2 , wherein the one field comprises at least one of a first value indicating that the command was successfully received by the corresponding memory device or a second value indicating that the command was not successfully received by the corresponding memory device.

4. The memory controller of claim 3 , wherein the combined acknowledgment status packet comprises a plurality of fields each comprising a logical combination of one field comprising acknowledgment information from one of the individual acknowledgement status packets and one or more fields comprising default values from one or more other individual acknowledgment status packets.

5. The memory controller of claim 4 , wherein to decode the combined acknowledgment status packet, the memory controller core is to determine which field of the plurality of fields in the combined acknowledgment status packet is associated with each of the plurality of memory devices.

6. The memory controller of claim 1 , wherein the logical combination is performed using a wired-OR connection.

7. The memory controller of claim 1 , wherein the plurality of memory devices comprises advanced random access memory (ARAM) devices.

8. A method comprising:
transmitting, by a memory controller, a memory command to a plurality of memory devices;
receiving, by a memory controller, a combined acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, wherein the combined acknowledgment status packet is formed from a logical combination of individual acknowledgment status packets corresponding to each of the plurality of memory devices, wherein each of the individual acknowledgment status packets comprises a plurality of fields, wherein each of the individual acknowledgement status packets comprises acknowledgment information associated with a corresponding memory device of the plurality of memory devices and stored in a respective designated field of the plurality of fields, and wherein a remainder of the plurality of fields in each individual acknowledgment status packet besides the respective designated field comprise default values, the acknowledgment information to indicate whether the command was successfully received by the corresponding memory device; and
decoding, by the memory controller, the combined acknowledgment status packet to identify the acknowledgement information corresponding to each of the plurality of memory devices.

9. The method of claim 8 , wherein each of the individual acknowledgment status packets comprises one field comprising acknowledgment information associated with the corresponding memory device and a plurality of fields comprising default values.

10. The method of claim 9 , wherein the one field comprises at least one of a first value indicating that the command was successfully received by the corresponding memory device or a second value indicating that the command was not successfully received by the corresponding memory device.

11. The method of claim 10 , wherein the combined acknowledgment status packet comprises a plurality of fields each comprising a logical combination of one field comprising acknowledgment information from one of the individual acknowledgement status packets and one or more fields comprising default values from one or more other individual acknowledgment status packets.

12. The method of claim 11 , wherein to decode the combined acknowledgment status packet, the memory controller core is to determine which field of the plurality of fields in the combined acknowledgment status packet is associated with each of the plurality of memory devices.

13. The method of claim 8 , wherein the logical combination is performed using a wired-OR connection.

14. The method of claim 8 , wherein the plurality of memory devices comprises advanced random access memory (ARAM) devices.

15. A memory device comprising:
a command interface to receive a memory command from a memory controller associated with the memory device; and
an acknowledgment interface to generate and transmit a combined acknowledgment status packet to the memory controller over a shared acknowledgment link coupled between the memory controller and the memory device, wherein the acknowledgment link is shareable by a plurality of memory devices associated with the memory controller, wherein the combined acknowledgment status packet is formed from a logical combination of individual acknowledgment status packets corresponding to each of the plurality of memory devices, wherein each of the individual acknowledgment status packets comprises a plurality of fields, wherein each of the individual acknowledgement status packets comprises acknowledgment information associated with a corresponding memory device of the plurality of memory devices and stored in a respective designated field of the plurality of fields, and wherein a remainder of the plurality of fields in each individual acknowledgment status packet besides the respective designated field comprise default values, the acknowledgment information to indicate whether the command was successfully received by the corresponding memory device.

16. The memory device of claim 15 , wherein each of the individual acknowledgment status packets comprises one field comprising acknowledgment information associated with the corresponding memory device and a plurality of fields comprising default values.

17. The memory device of claim 16 , wherein the one field comprises at least one of a first value indicating that the command was successfully received by the corresponding memory device or a second value indicating that the command was not successfully received by the corresponding memory device.

18. The memory device of claim 17 , wherein the combined acknowledgment status packet comprises a plurality of fields eac

Assignees

• Rambus Inc

Inventors

• Frans Yohan
• Li Simon
• Linstadt John Eric
• Kim Jun

Classifications

• H10F77/707 Primary

  of the substrates or of layers on substrates, e.g. textured ITO layer on a glass substrate · CPC title

• H01L31/02366 Primary

  Electricity · mapped topic

• G06F3/0613

  in relation to throughput · CPC title

• G06F3/0626

  Reducing size or complexity of storage systems · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title