Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11973108-B2
Application number	US-202018039610-A
Country	US
Kind code	B2
Filing date	Dec 1, 2020
Priority date	Dec 1, 2020
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

A semiconductor device includes: a drift region that is arranged on a main surface of a substrate, and has a higher impurity concentration than the substrate; a first well region that is connected to the drift region; and a second well region that is arranged adjacent to the first well region and faces the drift region. The second well region has a higher impurity concentration than the first well region. A distance between the source region that faces the drift region via the first well region and the drift region is greater than a distance between the second well region and the drift region, in a direction parallel to the main surface of the substrate. A depletion layer extending from the second well region reaches the drift region.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate;
a first-conductivity-type drift region that is selectively arranged on a main surface of the substrate, and has a higher impurity concentration than the substrate;
a second-conductivity-type first well region that is arranged above the main surface in a remaining region of the main surface other than a region in which the drift region is arranged, and that is connected to the drift region;
a second-conductivity-type second well region that is adjacent to the first well region along a thickness direction of the substrate, arranged on the remaining surface and faces the drift region, and has a higher impurity concentration than the first well region;
a first-conductivity-type source region that is connected to the first well region and the second well region, and faces the drift region via the first well region;
a first-conductivity-type drain region that is connected to the drift region at a position separated from the first well region and the second well region;
a gate insulating film that is arranged on surfaces of the drift region, the first well region, and the source region; and
a gate electrode that faces the drift region, the first well region, and the source region via the gate insulating film, wherein
a distance between the source region and the drift region is greater than a distance between the second well region and the drift region, in a direction parallel to the main surface of the substrate, and
a depletion layer extending from the second well region reaches the drift region.

2. The semiconductor device according to claim 1 , wherein
the gate insulating film is arranged in an inner wall surface of a groove in which side surfaces come into contact with the drift region, the first well region, and the source region, and lower ends reach the second well region, and
the gate electrode is arranged inside the groove.

3. The semiconductor device according to claim 1 , wherein
the substrate is a semi-insulating substrate or an insulating substrate.

4. The semiconductor device according to claim 1 , wherein
an end surface of the second well region comes into contact with an end surface of the drift region.

5. The semiconductor device according to claim 1 , wherein
a part of the second well region overlaps with a part of the drift region in planar view.

6. The semiconductor device according to claim 1 , wherein
the substrate is composed of a wide-bandgap semiconductor.

7. The semiconductor device according to claim 6 , wherein
the substrate is a silicon carbide substrate.

8. A method of manufacturing a semiconductor device comprising:
a step of selectivity forming on a main surface of a substrate, a first-conductivity-type drift region that has a higher impurity concentration than the substrate;
a step of forming a second-conductivity-type first well region above the main surface in a remaining region of the main surface other than a region in which the drift region is arranged, such that the first well region is connected to the drift region;
a step of forming a second-conductivity-type second well region having a higher impurity concentration than the first well region in the remaining region in such a way as to face the drift region, the second well region being adjacent to the first well region;
a step of forming a first-conductivity-type source region that is connected to the first well region and the second well region in such a way as to face the drift region via the first well region;
a step of forming a first-conductivity-type drain region that is connected to the drift region at a position separated from the first well region and the second well region;
a step of forming a gate insulating film on surfaces of the drift region, the first well region, and the source region; and
a step of forming a gate electrode that faces the drift region, the first well region, and the source region via the gate insulating film, wherein
a distance between the source region and the drift region is greater than a distance between the second well region and the drift region, in a direction parallel to the main surface of the substrate, and
a depletion layer extending from the second well region reaches the drift region.

Assignees

• Nissan Motor
• Renault Sas

Inventors

• Ni Wei
• Hayashi Tetsuya
• Numakura Keiichiro
• Marui Toshiharu
• TANAKA Ryouta
• Iwasaki Yuichi

Classifications

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D30/603 Primary

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D30/0289

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D12/031

  of IGBTs · CPC title