Embedded precision resistor for non-planar semiconductor device architectures

Patent metadata

Field	Value
Publication number	US-11973105-B2
Application number	US-201816145111-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

An integrated circuit structure comprises at least one metal gate formed in a first dielectric layer, the at least one metal gate comprising a workfunction layer and the gate oxide layer along sidewalls of the first dielectric layer. A field effect (FE) dielectric layer dielectric layer is above the first dielectric layer of the at least one metal gate. A precision resistor comprising a thin-film metallic material is formed on the FE dielectric layer above the at least one metal gate and extending laterally over the at least one metal gate.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a non-planar transistor comprising: a plurality of metal gates above a substrate and formed in a first dielectric layer, wherein the plurality of metal gates include a first set of one or more metal gates, a second set of one or more metal gates, and a third set of one or more metal gates, the third set of one or more metal gates located between the first set of one or more metal gates and the second set of one or more metal gates, ones of the plurality of metal gates comprising a workfunction layer and a gate oxide layer along sidewalls of the first dielectric layer, and respective source/drains, the respective source/drains formed between the first set of one or more metal gates and the third set of one or more metal gates, and between the third set of one or more metal gates and the second set of one or more metal gates;
a field effect (FE) inter-dielectric layer (ILD) formed over the first dielectric layer of the plurality of metal gates, the FE ILD comprising at least a bottom dielectric layer formed over and in contact with the first dielectric layer of the plurality of metal gates, and a top dielectric layer formed over the bottom dielectric layer;
a resistor comprising a thin-film metallic material over and on the bottom dielectric layer and extending over ones of the third set of one or more metal gates; and
a hardmask material over and on the resistor within the top dielectric layer.

2. The integrated circuit structure of claim 1 , wherein the thin-film metallic material is selected from the group comprising titanium nitride, tungsten, tantalum, tantalum nitride, titanium, aluminum, and cobalt.

3. The integrated circuit structure of claim 1 , wherein the precision resistor has a thickness of approximately 5-10 nm.

4. The integrated circuit structure of claim 1 , further comprising a first gate contact and a second gate contact formed through the FE ILD in contact with the precision resistor, wherein the first gate contact is aligned with a first one of the third set of one or more metal gates and the second gate contact is aligned with a second one of the third set of one or more metal gates.

5. The integrated circuit structure of claim 1 , further comprising first and second trench-shaped contacts (TCNs) formed through the FE ILD in contact with the respective source/drains and a gate contact (GCN) formed through the FE ILD in contact with a first one of the first set of one or more metal gates.

6. The integrated circuit structure of claim 1 , wherein the plurality of metal gates comprise a metal fill material selected from the group comprising metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, tungsten, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides.

Assignees

• Intel Corp

Inventors

• Ku Chieh-Jen
• Sell Bernhard
• Paulson Leif
• Phoa Kinyip
• Liu Shi

Classifications

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D86/85

  characterised by only passive components · CPC title