Semiconductor device and multiply-accumulate operation device

Patent metadata

Field	Value
Publication number	US-11972229-B2
Application number	US-201917040959-A
Country	US
Kind code	B2
Filing date	Mar 15, 2019
Priority date	Mar 30, 2018
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

Semiconductor devices and multiply-accumulate operation devices are disclosed. In one example, a semiconductor device includes synapses in which a nonvolatile variable resistance element taking a first resistance value and a second resistance value lower than the first resistance value and a fixed resistance element having a resistance value higher than the second resistance value are connected in series. An output line outputs a sum of currents flowing through the plurality of synapses.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a plurality of synapses each including
a nonvolatile variable resistance element taking a first resistance value and a second resistance value lower than the first resistance value,
a fixed resistance element connected in series with the nonvolatile variable resistance element, the fixed resistance element having a resistance value higher than the second resistance value, and
a selection transistor at a node between the variable resistance element and the fixed resistance element that controls selection or non-selection of the variable resistance element; and

an output line that outputs a sum of currents flowing through the plurality of synapses.

2. The semiconductor device according to claim 1 , wherein
the resistance value of the fixed resistance element is lower than the first resistance value.

3. The semiconductor device according to claim 2 , wherein
the resistance value of the fixed resistance element is lower than ⅕ of the first resistance value.

4. The semiconductor device according to claim 2 , wherein
a resistance value μ R of the fixed resistance element is 0.1μ<μ R <10μ when the first resistance value is μ off , the second resistance value is μ on , and μ=10{circumflex over ( )}{[log(μ off )+log(μ on )]/2}.

5. The semiconductor device according to claim 4 , wherein
σ R /μ R is smaller than σ on /μ on when a standard deviation of μ R is σ R and a standard deviation of μ on is σ on .

6. The semiconductor device according to claim 1 , wherein
the variable resistance element is a transistor.

7. The semiconductor device according to claim 6 , wherein
the variable resistance element is a ferroelectric transistor having a gate insulating film made of a ferroelectric material.

8. The semiconductor device according to claim 6 , wherein
the variable resistance element is an n-type transistor, and
the fixed resistance element is provided on an input side of the variable resistance element.

9. The semiconductor device according to claim 6 , wherein
the variable resistance element is a p-type transistor, and
the fixed resistance element is provided on an output side of the variable resistance element.

10. The semiconductor device according to claim 1 , wherein
the fixed resistance element is a tunnel resistance element formed by sandwiching an insulator with conductors.

11. The semiconductor device according to claim 10 , wherein
the fixed resistance element is a laminated tunnel resistance element in which a single layer or a plurality of layers of the insulator and the conductors are laminated.

12. The semiconductor device according to claim 6 , wherein
the fixed resistance element is provided in a contact that electrically connects a source or a drain of the transistor and a wiring layer.

13. The semiconductor device according to claim 6 , wherein the fixed resistance element is provided between wiring layers.

14. The semiconductor device according to claim 1 , wherein
the variable resistance element is a two-terminal-type variable resistance element.

15. The semiconductor device according to claim 1 , further comprising
a decoder that controls a resistance value of the variable resistance element of each of the plurality of synapses.

16. The semiconductor device according to claim 1 , wherein
the plurality of synapses are arrayed in a matrix.

17. The semiconductor device according to claim 1 , wherein
the plurality of synapses include a plurality of the variable resistance elements or the fixed resistance elements, and
the plurality of variable resistance elements or fixed resistance elements are connected in parallel.

18. The semiconductor device according to claim 1 , wherein
the plurality of synapses are further provided with a rectifying element.

19. A multiply-accumulate operation device comprising:
a plurality of synapses each including
a nonvolatile variable resistance element taking two values of a first resistance value and a second resistance value lower than the first resistance value,
a fixed resistance element connected in series with the nonvolatile variable resistance element, the fixed resistance element having a resistance value higher than the second resistance value, and
a selection transistor at a node between the variable resistance element and the fixed resistance element that controls selection or non-selection of the variable resistance element; and

an output line that outputs a sum of currents flowing through the plurality of synapses.

Assignees

• Sony Corp
• Sony Semiconductor Solutions Corp
• Sony Group Corp

Inventors

• Kobayashi Toshiyuki
• Morimoto Rui
• Okuno Jun
• Tsukamoto Masanori
• SHUTO Yusuke

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title