Failure characterization systems and methods for erasing and debugging programmable logic devices

Patent metadata

Field	Value
Publication number	US-11971992-B2
Application number	US-202017093578-A
Country	US
Kind code	B2
Filing date	Nov 9, 2020
Priority date	May 11, 2018
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.

First claim

What is claimed is:

1. A secure programmable logic device (PLD) failure characterization system, comprising:
a secure PLD, wherein the secure PLD comprises a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine, wherein the secure PLD is configured to perform a computer-implemented method comprising:
receiving a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O;
executing the FC command, wherein the executing the FC command comprises erasing and/or nullifying at least a portion of the NVM of the secure PLD to remove customer data associated with the configuration image;
loading a debug configuration into the PLD fabric while the portion of the NVM remains erased and/or nullified; and
performing a debug process, wherein the performing the debug process comprises booting the debug configuration by the PLD fabric that is configured to identify and/or characterize failures in the operation of any one or combination of elements of the secure PLD.

2. The secure PLD failure characterization system of claim 1 , wherein the computer-implemented method further comprises:
authenticating the received FC command prior to the executing the FC command, wherein the FC command is signed using an application private key associated with a secure PLD customer for the secure PLD, a corresponding application public key is stored in the NVM, and the authenticating comprises using the application public key to verify that the FC command is signed using the application private key associated with the secure PLD customer.

3. The secure PLD failure characterization system of claim 1 , wherein the computer-implemented method further comprises:
authenticating the received FC command prior to the executing the FC command, wherein the FC command comprises an FC trace ID, a trace ID associated the secure PLD is stored in the NVM, and the authenticating comprises comparing the FC trace ID with the trace ID stored in the NVM.

4. The secure PLD failure characterization system of claim 1 , wherein the NVM comprises rewritable and/or unlocked sectors, and wherein the executing the authenticated FC command comprises:
erasing individual sectors of the NVM according to a prioritized erase order, wherein the prioritized erase order comprises user flash memory sectors, image sectors, security and/or other features stored in securable storage sectors, device key sectors, and lock policy sectors.

5. The secure PLD failure characterization system of claim 1 , wherein the NVM comprises one time programmable sectors, and wherein the executing the authenticated FC command comprises:
nullifying individual sectors of the NVM according to a prioritized erase order, wherein the nullifying comprises setting all bits within a particular sector to “1,” and wherein the prioritized erase order comprises user flash memory sectors, image sectors, security and/or other features stored in securable storage sectors, device key sectors, and lock policy sectors.

6. The secure PLD failure characterization system of claim 1 , wherein the performing the debug process comprises:
receiving a debug configuration over the configuration I/O;
loading, booting, and/or executing the received debug configuration in the PLD fabric; and
generating a debug digest associated with the debug configuration, wherein the debug digest comprises a listing of failures and/or other debug information associated with execution of the debug configuration by the PLD fabric.

7. The secure PLD failure characterization system of claim 6 , wherein the performing the debug process further comprises:
authenticating the debug configuration prior to the loading, booting, and/or executing the received debug configuration in the PLD fabric; and
providing the debug digest to an external system coupled to the secure PLD over the configuration I/O.

8. The secure PLD failure characterization system of claim 1 , wherein the computer-implemented method further comprises re-provisioning the secure PLD after the performing the debug process, and wherein the re-provisioning the secure PLD comprises:
receiving a programming private key, a programming secret, and an initial programming image (IPI) configuration over the configuration I/O of the secure PLD
storing the IPI configuration in the NVM; and
programming the PLD fabric of the secure PLD according to the IPI configuration.

9. The secure PLD failure characterization system of claim 1 , further comprising:
an external system comprising a processor and a memory and configured to be coupled to the secure PLD through the configuration input/output (I/O) of the secure PLD, wherein the memory comprises machine-readable instructions which when executed by the processor of the external system are adapted to cause the external system to:
provide a debug configuration to the secure PLD over the configuration I/O;
receive a debug digest from the secure PLD associated with booting and/or execution of the debug configuration by the PLD fabric of the secure PLD;
determine an updated manufacturer trim based, at least in part, on the received debug digest; and
provide the updated manufacturer trim to the secure PLD over the configuration I/O.

10. The secure PLD failure characterization system of claim 1 , further comprising:
an external system comprising a processor and a memory and configured to be coupled to the secure PLD through the configuration input/output (I/O) of the secure PLD, wherein the memory comprises machine-readable instructions which when executed by the processor of the external system are adapted to cause the external system to:
generate or receive a protected configuration for the secure PLD; and
program the secure PLD according to the protected configuration;
wherein the protected configuration comprises an application configuration and a feature configuration, each signed by an application private key associated with a secure PLD customer and encrypted by an application encryption key associated with the secure PLD customer, and a programming key digest comprising an encrypted and signed combination of an application public key, the application encryption key, and a programming secret associated with the secure PLD customer.

11. A secure programmable logic device (PLD) failure characterization system, comprising:
an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD, wherein the memory comprises machine-readable instructions which when executed by the processor of the external system are adapted to cause the external system to perform a computer-implemented method comprising:
providing a failure characterization (FC) command and/or a debug configuration to the secure PLD over the configuration I/O; and
receiving a debug digest from the secure PLD associated with booting and/or execution of the debug configuration by a PLD fabric of the secure PLD;
determining an updated manufacturer trim based, at least in part, on the received debug digest; and
providing the updated manufacturer trim to the secure PLD over the configuration I/O.

12. The secure PLD failure characterization system of claim 11 , further comprising:
the secure PLD, wherein the secure PLD comprises a plurality of programmable logic blocks (

Assignees

• Lattice Semiconductor Corp

Inventors

• Zhang Fulong
• Chandra Srirama
• Hegade Sreepada
• Coplen Joel
• Han Wei
• Sun Yu

Classifications

• G06F21/575 Primary

  Secure boot · CPC title

• G06F8/65

  Updates (security arrangements therefor G06F21/57) · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F11/3656

  using a specific debug interface · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title