Methods, devices and systems for high speed transactions with nonvolatile memory on a double data rate memory bus

Patent metadata

Field	Value
Publication number	US-11971832-B2
Application number	US-202017125927-A
Country	US
Kind code	B2
Filing date	Dec 17, 2020
Priority date	Oct 7, 2020
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

First claim

What is claimed is:

1. An integrated circuit (IC) device, comprising:
a first command-address (CA) bus input that includes a plurality of first parallel CA inputs;
a second CA bus input that includes a plurality of second parallel CA inputs;
a plurality of nonvolatile memory (NVM) cell arrays;
a first command decoder configured to detect commands received at the first CA bus input[s], including express read (NVR) command sequences,
a second command decoder configured to detect commands received at the second CA bus input, including NVR command sequences,
each NVR command sequence including no more than two consecutive NVR read commands distinguishable from other read commands by bit values of the NVR command, and
each NVR command sequence terminates with a receipt of a command that is not an NVR command or an end to a receipt of consecutive NVR read commands;

first access circuits configured to access a first of the NVM cell arrays and output first read data in response to a first NVR command sequence received on the first CA input;
second access circuits configured to access a second of the NVM cell arrays and output second read data in response to a second NVR command sequence received on the second CA bus input; and
a data bus input/output (I/O) including a plurality of parallel data I/Os configured to receive the first read data and second read data in synchronism with rising and falling edges of a timing clock; wherein
the second NVR command sequence follows the first NVR command sequence with no intervening command data, and
the second read data follows the first read data with no intervening read data.

2. The IC device of claim 1 , wherein:
the first and second CA bus inputs each include[s] six CA inputs coupled to a CA bus; and
the CA bus and data bus I/O are compatible with the LPDDR4 physical interface standard.

3. The IC device of claim 1 , wherein:
all address data for accessing the first read data are included in the first NVR command sequence; and
all address data for accessing the second read data are included in the second NVR command sequence.

4. The IC device of claim 1 , wherein:
the NVR read commands include bit value locations corresponding to bit value locations of commands compatible with the LPDDR4 standard, and
at least one NVR read command includes address data at a bit location where an LPDDR4 compatible command includes command data.

5. The IC device of claim 1 , wherein:
each NVR read command is received at one of the CA bus inputs over an integer multiple of two cycles of the timing clock, the integer being greater than or equal to one.

6. The IC device of claim 1 , further including:
a first serial bus input including at least one serial I/O line configured to receive first serial command and address data; and
the first access circuits are configured to access at least the first NVM cell array in response to first serial command and address data.

7. The IC device of claim 6 , further including:
a second serial bus input including at least one serial I/O line configured to receive second serial command and address data; and
the second access circuits are configured to access at least the second NVM cell array in response to the second serial command and address data.

8. The IC device of claim 1 , wherein:
the first read data and the second read data have a burst length (BL) that is configurable to one of a plurality of BL values, at least one BL value being no more than eight.

9. The IC device of claim 1 , wherein:
the first CA bus input, first command decoder, the first NVM cell array and the first access circuits are formed with a first IC substrate;
the second CA bus input, the second command decoder, the second NVM cell array and the second access circuits are formed with a second IC substrate; and
the first and second IC substrates are commonly coupled to the data bus IO.

10. The IC device of claim 9 , wherein:
the first and second IC substrates are formed in a same IC package.

11. The IC device of claim 9 , wherein:
the first and second IC substrates are formed in different IC packages.

12. The IC device of claim 1 , wherein:
the first and second NVR command sequences are data transfers to a same cache line of cache memory.

13. The IC device of claim 12 , wherein:
the first read data and second read data are each bursts of eight data values that include 16 bytes of data; and
the cache line stores 32 bytes of data.

Assignees

• Infineon Technologies LLC

Inventors

• Zitlaw Clifford
• Rosner Stephan
• Van Antwerpen Hans
• Whately Morgan Andrew

Classifications

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/409

  Mechanical coupling (back panels H05K7/1438) · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title