Electronic tester and testing method

US11971450B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11971450-B2
Application numberUS-202117540496-A
CountryUS
Kind codeB2
Filing dateDec 2, 2021
Priority dateDec 2, 2021
Publication dateApr 30, 2024
Grant dateApr 30, 2024

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides an electronic tester comprising at least one test fixture that couples to a device under test, at least one test instrument coupled to at least one of the test fixtures that measures signals in the device under test, a test controller that controls the device under test while the test is performed, and an adapter module comprising a general control interface that is coupled to the test controller, and a DUT-specific communication interface that couples to the device under test to communicate with the device under test, wherein the test controller controls the device under test with generic control signals sent to the general control interface, and wherein the adapter module translates the general control signals into DUT-specific control signals and transmit the DUT-specific control signals to the device under test. Further, the present disclosure provides a respective method.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic tester comprising: at least one test fixture that couples to a device under test; at least one test instrument coupled to at least one of the test fixtures that measures signals in the device under test via the at least one of the test fixtures; a test controller that controls the device under test while the test is performed; and an adapter module comprising a general control interface that is coupled to the test controller, and a DUT-specific communication interface that couples to the device under test to communicate with the device under test; wherein the test controller controls the device under test with generic control signals sent to the general control interface; wherein the adapter module translates the generic control signals into DUT-specific control signals and transmits the DUT-specific control signals to the device under test; and wherein the test controller comprises an adapter identifier that identifies the adapter module and determines which of the generic control signals of all generic control signals that the test controller may generate are compatible with the adapter module. 2. The electronic tester according to claim 1 , wherein the adapter module comprises a computer program product comprising computer readable instructions that are executed by a processor of the test controller. 3. The electronic tester according to claim 1 , wherein the adapter module comprises: a hardware module; wherein the general control interface comprises a first hardware interface on the hardware module for coupling to the test controller; and wherein the DUT-specific communication interface comprises a second hardware interface on the hardware module for coupling to the device under test. 4. The electronic tester according to claim 3 , wherein the adapter module comprises: an adapter controller that receives the generic control signals and translates the received generic control signals into the DUT-specific control signals. 5. The electronic tester according to claim 1 , wherein the test controller is provided in one of the at least one test instrument. 6. The electronic tester according to claim 5 , wherein the adapter module is provided in the test instrument that carries the test controller. 7. The electronic tester according to claim 1 , further comprising a test sequence memory comprising for each one of a plurality of test sequences respective generic control signals that form the respective test sequence. 8. The electronic tester according to claim 1 , further comprising a test sequence memory comprising for each one of a plurality of test sequences respective generic control signals that form the respective test sequence. 9. The electronic tester according to claim 8 , wherein the test controller determines if all generic control signals used in a test sequence that is to be executed are compatible with the identified adapter module and provides a warning signal if not all of the generic control signals used in the respective test sequence are compatible with the identified adapter module. 10. A method for testing a device under test, the method comprising: coupling at least one test fixture to the device under test; measuring signals in the device under test with at least one test instrument coupled to the device under test via the at least one of the test fixtures; coupling an adapter module via a general control interface with a test controller, and via a DUT-specific communication interface with the device under test to communicate with the device under test; providing, from the test controller, generic control signals to the general control interface for controlling the device under test; translating the generic control signals into DUT-specific control signals with the adapter module; transmitting the DUT-specific control signals to the device under test; and identifying the adapter module and determining which of the generic control signals of all generic control signals that the test controller may generate are compatible with the adapter module. 11. The method according to claim 10 , wherein the adapter module comprises computer readable instructions that are executed by a processor of the test controller. 12. The method according to claim 10 , wherein the adapter module comprises: a hardware module; wherein the general control interface comprises a first hardware interface on the hardware module that is coupled to the test controller; and wherein the DUT-specific communication interface comprises a second hardware interface on the hardware module that is coupled to the device under test. 13. The method according to claim 12 , further comprising: with an adapter controller of the adapter module receiving the generic control signals and translating the received generic control signals into the DUT-specific control signals. 14. The method according to claim 10 , wherein the test controller is provided in one of the at least one test instrument. 15. The method according to claim 14 , wherein the adapter module is provided in the test instrument that carries the test controller. 16. The method according to claim 10 , further comprising storing in a test sequence memory for each one of a plurality of test sequences respective generic control signals that form the respective test sequence. 17. The method according to claim 10 , further comprising storing in a test sequence memory for each one of a plurality of test sequences respective generic control signals that form the respective test sequence. 18. The method according to claim 17 , comprising determining if all generic control signals used in a test sequence that is to be executed are compatible with the identified adapter module and providing a warning signal if not all of the generic control signals used in the respective test sequence are compatible with the identified adapter module.

Assignees

Inventors

Classifications

  • Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture · CPC title

  • computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging · CPC title

  • Tester/user interface · CPC title

  • Complete testing stations; systems; procedures; software aspects · CPC title

  • Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title

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Frequently asked questions

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What does patent US11971450B2 cover?
The present disclosure provides an electronic tester comprising at least one test fixture that couples to a device under test, at least one test instrument coupled to at least one of the test fixtures that measures signals in the device under test, a test controller that controls the device under test while the test is performed, and an adapter module comprising a general control interface that…
Who is the assignee on this patent?
Rohde & Schwarz
What technology area does this patent fall under?
Primary CPC classification G01R31/31905. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 30 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).