Chamfering apparatus and method for manufacturing notchless wafer
US-2016300708-A1 · Oct 13, 2016 · US
Wafer manufacturing method and wafer
US11969856B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11969856-B2 |
| Application number | US-201917418087-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 8, 2019 |
| Priority date | Dec 27, 2018 |
| Publication date | Apr 30, 2024 |
| Grant date | Apr 30, 2024 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A manufacturing method of a wafer with a notch includes: polishing principal surfaces of the wafer; mirror-polishing a notch chamfered portion of the notch; mirror-polishing an outer-periphery chamfered portion of an outer peripheral portion of the wafer; and finish-polishing one of principal surfaces of the wafer, the finish-polishing being performed after performing the mirror-polishing of the notch chamfered portion, the polishing of the principal surfaces, and the mirror-polishing of the outer-periphery chamfered portion in this order.
First claim
Opening claim text (preview).
The invention claimed is: 1. A manufacturing method of a wafer comprising a notch, the method comprising: mirror-polishing a notch chamfered portion of the notch in a manner such that polishing progresses while a polishing pad extends over a first principal surface and a second principal surface of the wafer; polishing the first and second principal surfaces of the wafer; mirror-polishing an outer-periphery chamfered portion of an outer periphery of the wafer; and finish-polishing the first principal surface of the wafer, wherein the finish-polishing is performed after performing the mirror-polishing of the notch chamfered portion, the polishing of the first and second principal surfaces, and the mirror-polishing of the outer periphery chamfered portion in this order. 2. The manufacturing method of a wafer according to claim 1 , wherein the wafer is a silicon wafer. 3. A wafer comprising a notch, wherein an edge roll-off amount of a notch chamfered portion of the notch is smaller than an edge roll-off amount of an outer-periphery chamfered portion of an outer peripheral portion of the wafer.
Assignees
Inventors
Classifications
by polishing · CPC title
- H10P90/128Primary
by edge treatment, e.g. chamfering · CPC title
- H10P90/123Primary
by grinding or lapping · CPC title
- B24B37/042Primary
operating processes therefor · CPC title
Electricity · mapped topic
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- What does patent US11969856B2 cover?
- A manufacturing method of a wafer with a notch includes: polishing principal surfaces of the wafer; mirror-polishing a notch chamfered portion of the notch; mirror-polishing an outer-periphery chamfered portion of an outer peripheral portion of the wafer; and finish-polishing one of principal surfaces of the wafer, the finish-polishing being performed after performing the mirror-polishing of th…
- Who is the assignee on this patent?
- Sumco Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P90/128. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 30 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).