Computing apparatus, image capturing apparatus, control method, and storage medium

Patent metadata

Field	Value
Publication number	US-11968469-B2
Application number	US-202217883694-A
Country	US
Kind code	B2
Filing date	Aug 9, 2022
Priority date	Aug 20, 2021
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

An apparatus comprises a circuitry, a temporary memory and a permanent memory storing necessary information for executing each of a plurality types of processing. The apparatus receives a switching instruction and switches processing executed by the circuitry by varying the necessary information in response to reception of the instruction. The information is read out and loaded into a first region of the temporary memory. If the circuitry is executing at least one of the plurality types of processing when the instruction is made, the apparatus switches the circuitry to a state of being capable of executing the processing by reading out the information of the processing, loading the information into a second region of the temporary memory, and moving or copying the information related to the processing from the second region to the first region in response to the executing processing ending.

First claim

What is claimed is:

1. A computing apparatus capable of executing a plurality of types of processing, the computing apparatus comprising:
at least one processor and/or circuitry configured to execute at least one of the plurality of types of processing;
a temporary memory; and
a permanent memory configured to store necessary information for executing each of the plurality of types of processing and instructions that, when executed by the at least one processor and/or circuitry, cause the at least one processor and/or circuitry to function as:
a receiving unit configured to receive a switching instruction for switching processing; and
a switching unit configured to switch processing executed by the at least one processor and/or circuitry by varying the necessary information in response to reception of the switching instruction, the necessary information being read out from the permanent memory and loaded into a first region of the temporary memory,

wherein if the at least one processor and/or circuitry is executing at least one of the plurality of types of processing when the switching instruction is made, the switching unit switches the at least one processor and/or circuitry to a state of being capable of executing processing to be switched to by reading out, from the permanent memory, the necessary information related to the processing to be switched to, loading the necessary information into a second region of the temporary memory different from the first region, and moving or copying the necessary information related to the processing to be switched to from the second region to the first region in response to the processing being executed ending,
the necessary information includes information for changing content of at least some computation processing in the processing executed by the at least one processor and/or circuitry, the at least some computation processing including inference processing using an inference model, and
in a case where executing at least one of the plurality of types of processing, the at least one processor and/or circuitry executes the at least some computation processing using the necessary information loaded into the first region.

2. The computing apparatus according to claim 1 ,
wherein
the necessary information includes information that constitutes the inference model when loaded into the first region.

3. The computing apparatus according to claim 2 ,
wherein if the inference processing using the inference model loaded into the first region is being executed when the switching instruction is made, the switching unit loads information that constitutes the inference model used in the processing to be switched to into the second region.

4. The computing apparatus according to claim 1 ,
wherein the computing apparatus is a reconfigurable computing apparatus,
the necessary information is information for reconfiguring a logical operation structure of the at least one processor and/or circuitry, and
the switching unit causes the at least one processor and/or circuitry to be reconfigured based on the necessary information related to the processing to be switched to being moved or copied from the second region to the first region in response to the processing being executed ending.

5. The computing apparatus according to claim 1 ,
wherein the permanent memory further stores instructions that, when executed by the at least one processor and/or circuitry, cause the at least one processor and/or circuitry to function as a management unit configured to manage a usage state of the second region,
wherein the receiving unit receives at least one switching instruction related to processing executed sequentially, the at least one switching instruction being the switching instruction, and
if the at least one processor and/or circuitry is executing at least one of the plurality of types of processing when the at least one switching instruction is received, the switching unit varies a loading form, in which the necessary information is loaded into the second region, of the necessary information corresponding to the at least one switching instruction, according to the usage state of the second region.

6. The computing apparatus according to claim 1 ,
wherein each of the plurality of types of processing is analysis processing on an input image, and
wherein the permanent memory further stores instructions that, when executed by the at least one processor and/or circuitry, cause the at least one processor and/or circuitry to function as a first obtainment unit configured to obtain the input image and store the input image in a third region of the temporary memory.

7. An image capturing apparatus to which the computing apparatus according to claim 6 is detachably connected, the image capturing apparatus comprising:
an image capturing unit configured to output a captured image;
at least one processor and/or circuitry; and
a memory storing instructions that, when executed by the at least one processor and/or circuitry, cause the at least one processor and/or circuitry to function as:
a determination unit configured to determine a plurality of instances of analysis processing to be executed on the captured image by the computing apparatus and an order of the plurality of instances of analysis processing;
a first input unit configured to input the captured image to the computing apparatus as the input image;
a second input unit configured to sequentially input execution instructions for the plurality of instances of analysis processing and the switching instruction to the computing apparatus based on the order determined by the determination unit; and
a second obtainment unit configured to obtain an analysis result of the plurality of instances of analysis processing by the computing apparatus.

8. The image capturing apparatus according to claim 7 ,
wherein the permanent memory further stores instructions that, when executed by the at least one processor and/or circuitry, cause the at least one processor and/or circuitry to function as a dividing unit configured to divide the captured image into a plurality of regions,
the first input unit inputs the input image in a form of divided images obtained by the dividing performed by the dividing unit,
the second input unit further inputs, to the computing apparatus, a write instruction to write into the third region of the temporary memory of the computing apparatus when the divided images are input by the first input unit, and
when obtaining an analysis result of the plurality of instances of analysis processing is prioritized for a predetermined one of the divided images, the determination unit determines the order such that the write instruction for inputting another of the divided images is not included until after the execution instructions for the plurality of instances of analysis processing and the switching instruction, related to the predetermined one of the divided images, are complete following the write instruction for inputting the predetermined one of the divided images.

9. The image capturing apparatus according to claim 7 ,
wherein the computing apparatus is a recording apparatus of the SD standard, and
the first input unit, the second input unit, and the second obtainment unit are compliant with a communication standard of the SD standard.

10. A control method for a computing apparatus capable of executing a plurality of types of processing,
wherein the computing apparatus comprises:
a at least one processor and/or circuitry configured to execute at least one of the plurality of types of processing;
a temporary memory; and
a permanent memory configured to store necessary information for executing each of

Assignees

• Canon Kk

Inventors

• Maeda Ryo

Classifications

• H04N5/268 Primary

  Signal distribution or switching · CPC title

• H04N23/80 Primary

  Camera processing pipelines; Components thereof · CPC title

• H04N23/61

  based on recognised objects · CPC title

• H04N23/665

  involving internal camera communication with the image sensor, e.g. synchronising or multiplexing SSIS control signals · CPC title