Signal shaping for compensation of metastable errors

Patent metadata

Field	Value
Publication number	US-11967967-B2
Application number	US-202217807454-A
Country	US
Kind code	B2
Filing date	Jun 17, 2022
Priority date	Jun 17, 2022
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

First claim

What is claimed is:

1. A circuit comprising:
a digital circuit including a digital output for producing a series of digital signal values;
a first data path from the digital output, the first data path including an analog delay circuit, the first data path for producing a first analog delay signal from the digital output the digital circuit;
a second data path from the digital output, the second data path including a digital delay circuit and a digital to analog converter for producing a second analog delay signal from the digital output of the digital circuit;
an analog circuit output for producing an analog output signal having values over time corresponding to the digital signal values of the series, wherein the first analog delay signal and the second analog delay signal are used to adjust a later analog output signal value of the analog output signal that is produced by the analog circuit output subsequent to a former analog output signal value of the analog output signal produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error.

2. The circuit of claim 1 further comprising:
a digital to analog circuit coupled to the digital output of the digital circuit for producing an analog signal from the digital output of the digital circuit;
wherein the analog output signal is produced from the analog signal where the analog signal is modified using the first analog delay signal and the second analog delay signal to adjust the later analog output signal value of the analog output signal that is produced by the analog circuit output.

3. The circuit of claim 1 comprising:
a combiner circuit, the combiner circuit including a first input to receive the first analog delay signal and a second input to receive the second analog delay signal, the combiner circuit performing a combining operation to produce a first analog signal from the first analog delay signal and the second analog delay signal, wherein the first analog signal is used to adjust the later analog output signal value of the analog output signal that is produced by the analog circuit output.

4. The circuit of claim 3 wherein the combining operation includes subtracting the first analog delay signal from the second analog delay signal.

5. The circuit of claim 3 further comprising a filter including an input to receive the first analog signal and an output to provide a filtered first signal, wherein the filtered first signal is used to adjust the later analog output signal value that is produced by the analog circuit output.

6. The circuit of claim 5 further comprising a second combiner circuit including a first input to receive the filtered first signal and a second input coupled to an output of a digital to analog circuit whose input is coupled to the digital output of the digital circuit for producing an analog signal from the digital output of the digital circuit, the second combiner circuit performing a combining operation to produce the analog output signal from the filtered first signal and the analog signal from the output of the digital to analog circuit whose input is coupled to the output of the digital circuit.

7. The circuit of claim 1 wherein the first analog delay signal is subtracted from the second analog delay signal in adjusting the later analog output signal value of the analog output signal.

8. The circuit of claim 1 further comprising a combiner circuit, the combiner circuit including a first input to receive the first analog delay signal, a second input to receive the second analog delay signal, a third input coupled to an output of a digital to analog circuit whose input is coupled to the output of the digital circuit for producing an analog signal from the digital output of the digital circuit, the combiner circuit performing a combining operation to produce the analog output signal from the first analog delay signal, the second analog delay signal, and the analog signal from the output of the digital to analog circuit whose input is coupled to the output of the digital circuit.

9. The circuit of claim 8 wherein the third input is coupled to an output of a digital to analog circuit of the first data path.

10. The circuit of claim 8 wherein the combining operation includes subtracting the first analog delay signal from the second analog delay signal and the analog signal from the output of the digital to analog circuit whose input is coupled to the output of the digital circuit.

11. The circuit of claim 1 wherein the digital circuit is an analog to digital converter.

12. The circuit of claim 11 wherein the analog to digital converter includes an input to receive an analog signal, wherein the analog output signal is used to adjust the analog signal.

13. The circuit of claim 12 further comprising:
a filter circuit to filter the analog signal that has been adjusted;
wherein output of the filter circuit is coupled to an input of the digital to analog converter.

14. The circuit of claim 1 wherein the first data path includes a second digital to analog converter located in the first data path before the analog delay circuit.

15. The circuit of claim 1 wherein the first data path includes a second digital to analog converter located in the first data path after the analog delay circuit, the second digital to analog converter for producing the first analog delay signal.

16. The circuit of claim 15 wherein the analog delay circuit is a multibit analog delay circuit.

17. The circuit of claim 1 wherein the first analog delay signal and the second analog delay signal are each characterized as differential signals.

18. The circuit of claim 1 further comprising:
a multistage pipelined analog to digital converter circuit, wherein the digital circuit, the first data path, the second data path, and the analog circuit output are part of a stage of the multistage pipelined analog to digital converter circuit.

19. The circuit of claim 1 wherein the second data path is configured to convert a digital signal value with a metastable error to a digital signal value without a metastable error.

20. A circuit comprising:
a digital circuit including a digital output for producing a series of digital signal values;
a first data path from the digital output, the first data path including an analog delay circuit, the first data path for producing a first analog delay signal from the digital output the digital circuit;
a second data path from the digital output, the second data path including a digital delay circuit and a digital to analog converter for producing a second analog delay signal from the digital output of the digital circuit;
an analog circuit output for producing an analog output signal having values over time corresponding to the digital signal values of the series, wherein the first analog delay signal and the second analog delay signal are used to adjust an analog output signal value of the analog output signal that is produced by the analog circuit output if the first analog delay signal is different from the second analog delay signal.

Assignees

• Nxp Bv

Inventors

• Liu Qilong
• Bajoria Shagun
• Breems Lucien Johannes

Classifications

• H03M1/0604 Primary

  at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/0626

  by filtering · CPC title

• H03M1/0687

  using fault-tolerant coding, e.g. parity check, error correcting codes (H03M1/069 takes precedence) · CPC title

• H03M1/502

  using tapped delay lines · CPC title

• H03K5/06 Primary

  by the use of delay lines or other analogue delay elements · CPC title