Thin film transistor, method of manufacturing the same and display device

Patent metadata

Field	Value
Publication number	US-11967620-B2
Application number	US-202217682239-A
Country	US
Kind code	B2
Filing date	Feb 28, 2022
Priority date	Jun 6, 2018
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

Embodiments of the present disclosure provide a thin film transistor, a method of manufacturing the same, and a display device. The thin film transistor includes a metal conductive pattern layer, an interlayer insulating layer, and a metal oxide layer; and the metal conductive pattern layer includes: a light shielding pattern, a source signal line, and/or a drain signal line; the metal oxide layer includes: a source electrode, a drain electrode, and an active layer. An orthographic projection of the active layer on the base substrate has an overlapping region with that of the light shielding pattern; the source electrode extends through the interlayer insulating layer to connect to the source signal line, and/or the drain electrode extends through the interlayer insulating layer to connect to the drain signal line.

First claim

The invention claimed is:

1. An array substrate, the array substrate is an OLED array substrate; and a sub-pixel of the array substrate includes a pixel driving circuit, wherein the pixel driving circuit comprises:
a driving transistor, and an organic light emitting diode connected to a source electrode of the driving transistor; and a drain electrode of the driving transistor is connected to a drain signal line, and the source electrode of the driving transistor is connected to a first electrode of the organic light emitting diode;
a first switching transistor, a second switching transistor, and a storage capacitor, wherein a drain electrode of the first switching transistor is connected to a data line, a source electrode of the first switching transistor is connected to a gate electrode of the driving transistor, and a gate electrode of the first switching transistor is connected to a first gate line; a gate electrode of the second switching transistor is connected to a second gate line, a source electrode of the second switching transistor is connected to a sensing signal line, and a drain electrode of the second switching transistor is connected to the source electrode of the driving transistor; one end of the storage capacitor is connected to the gate electrode of the driving transistor, and the other end is connected to the source electrode of the driving transistor,
wherein the source electrode of the first switching transistor is connected to the gate electrode of the driving transistor through a connection portion,
wherein the first electrode is a transparent electrode; and the connection portion is made of a same material and located in a same layer as the first electrode.

2. The array substrate of claim 1 , wherein the driving transistor is a thin film transistor comprising: a metal conductive pattern layer disposed on a base substrate; and an interlayer insulating layer, a metal oxide layer, a gate insulating layer, and the gate electrode, which are sequentially disposed on the base substrate having the metal conductive pattern layer;
wherein the metal conductive pattern layer includes: a light shielding pattern, a source signal line, and/or the drain signal line;
the metal oxide layer includes the source electrode, the drain electrode, and an active layer between the source electrode and the drain electrode and being in direct contact with the source electrode and the drain electrode;
an orthographic projection of the active layer on the base substrate has an overlapping region with an orthographic projection of the light shielding pattern on the base substrate; and
the source electrode extends through the interlayer insulating layer to connect to the source signal line, and/or the drain electrode extends through the interlayer insulating layer to connect to the drain signal line.

3. The array substrate of claim 2 , wherein
the source electrode, the drain electrode, and an active layer of the first switching transistor and the source electrode, the drain electrode, and an active layer of the second switching transistor are respectively made of a same material and located in a same layer as the source electrode, the drain electrode, and the active layer of the driving transistor; and
the gate electrode of the first switching transistor and the gate electrode of the second switching transistor are both made of a same material and located in a same layer as the gate electrode of the driving transistor.

4. The array substrate as claimed in claim 2 , wherein
the source electrode of the driving transistor is connected to the light shielding pattern through the source signal line;
the source electrode of the driving transistor and the drain electrode of the second switching transistor constitute an integral electrode, and the integral electrode is connected to the first electrode; and
the connection portion extends to a position facing the integral electrode to form the storage capacitor with the integral electrode.

5. The array substrate as claimed in claim 3 , wherein
the data line is located in a same layer and made of a same material as the light shielding pattern of the driving transistor; and/or
the first gate line, the second gate line, and the sensing signal line are located in a same layer and made of a same material as the gate electrode of the driving transistor.

6. The array substrate as claimed in claim 4 , wherein an orthographic projection of the connection portion on the base substrate covers the orthographic projection of the light shielding pattern on the base substrate.

7. The array substrate as claimed in claim 3 , wherein a passivation layer and a planarization layer are sequentially provided on a side of the gate electrode of the first switching transistor, the gate electrode of the second switching transistor and the gate electrode of the driving transistor away from the base substrate, and the source electrode of the first switching transistor and the gate electrode of the driving transistor are connected by the connection portion through via holes in the passivation layer and the planarization layer.

8. The array substrate as claimed in claim 2 , wherein the orthographic projection of the light shielding pattern on the base substrate covers the orthographic projection of the active layer on the base substrate.

9. The array substrate as claimed in claim 2 , wherein the light shielding pattern is connected to the source signal line; or
the light shielding pattern is connected to the drain signal line.

10. The array substrate as claimed in claim 2 , wherein the active layer is made of a metal oxide constituting the metal oxide layer, and the source electrode of the driving transistor and the drain electrode of the driving transistor include a metal that is transformed from the metal oxide by a conductor transforming process.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Xu Pan
• Lin Yicheng
• Gai Cuili
• Wang Ling
• Li Yongqian

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title