Use of multiple different variants of floating point number formats in floating point operations on a per-operand basis

Patent metadata

Field	Value
Publication number	US-11966740-B2
Application number	US-202117444788-A
Country	US
Kind code	B2
Filing date	Aug 10, 2021
Priority date	Oct 7, 2020
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

A processor comprising: a register file comprising a group of operand registers for holding data values, each operand register being a fixed number of bits in length for holding a respective data value of that length; and processing logic comprising floating point logic for performing floating point operations on data values in the register file, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point format comprising a set of mantissa bits and a set of exponent bits. The processing logic is operable to select between a plurality of different variants of the floating point format, at least some of the variants having a different size sets of mantissa bits and exponent bits relative to one another.

First claim

The invention claimed is:

1. A processor comprising:
at least one register file comprising a group of operand registers for holding data values loaded from memory or to be stored back to memory, each operand register being a fixed number of bits in length for holding a respective data value of the length; and
processing logic comprising floating point logic for performing floating point operations on data values in the at least one register file, wherein the floating point logic is configured to perform each of the floating point operations in response to execution of a single instance of a respective type of machine code instruction in an instruction set of the processor, whereby for a respective data value held in each operand register upon which one of the floating point operations is to be performed, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point number format comprising a set of mantissa bits and a set of exponent bits;
wherein the processing logic is operable to select a selected variant of the floating point number format from among a plurality of different variants of the floating point number format, at least some of the variants having different size sets of mantissa bits and exponent bits relative to one another;
wherein a same one of the floating point operations, performed in response to execution of a same, single instance of a same one of said types of machine code instruction, operates on a first one of the data values from a first of the group of operand registers and on a second one of data values from a second of the group of operand registers other than the first operand register, and wherein the floating point logic is operable to apply first of the plurality of different variants of the floating point number format to the first data value in the first operand register and a second of the plurality of different variants of the floating point number format to the second data value in the second operand register as operated on by the same floating point operation;
wherein the processor further includes a first control register for holding a first programmable setting and a second control register for holding a second programmable setting, the first programmable setting in the first control register and the second programmable setting in the second control register being programmable by one or more earlier instructions executed on the processor,
wherein the first variant of the floating point number format applied to the first data value in the first operand register is programmable via the first programmable setting in the first control register and the second variant of the floating point number format applied to the second data value in the second programmable register is via the second programmable setting in the second control register, and
wherein the first and second programmable settings in the first and second control registers, respectively, are programmable independently of one another, thereby enabling the first and second variants to be selected independently of one another for the same floating point operation.

2. The processor of claim 1 , wherein the plurality of different variants comprise one variant where the size of the set of exponent bits is zero, and at least one other variant where both the size of the set of exponent bits is non-zero and the size of the set of mantissa bits is non-zero.

3. The processor of claim 1 , wherein the plurality of different variants comprise one variant where the size of the set of mantissa bits is zero, and at least one other variant where both the size of the set of mantissa bits is non-zero and the size of the set of exponent bits is non-zero.

4. The processor of claim 1 , wherein at least one of the plurality of different variants of the floating point number format further comprises a single sign bit.

5. The processor of claim 4 , wherein the plurality of different variants comprise at least one variant having a single sign bit and at least one variant having no sign bit.

6. The processor of claim 4 , wherein the plurality of different variants consist of all possible combinations of the sizes of the sets of mantissa and exponent bits filling the fixed number of bits with the sign bit, mantissa and exponent bits; ranging from one sign bit, zero exponent bits and the rest as mantissa bits; to one sign bit, zero mantissa bits and the rest as exponent bits.

7. The processor of claim 4 , wherein the fixed number of bits in length for each operand register in the group is eight bits; and wherein the plurality of different variants consist of all possible combinations filing the fixed number of bits, from zero exponent bits and seven mantissa bits, to zero mantissa bits and seven exponent bits.

8. The processor of claim 4 , wherein the fixed number of bits in length for each operand register in the group is sixteen bits; and wherein the variants comprise two of more of the following:
five exponent bits and ten mantissa bits,
six exponent bits and nine mantissa bits,
seven exponent bits and eight mantissa bits, and/or
eight exponent bits and seven mantissa bits.

9. The processor of claim 4 , wherein according to the floating point number format the respective value in binary is defined as:
(−1){circumflex over ( )}S×(M+1)×2{circumflex over ( )}(E−b),

where S is the sign bit, M is the mantissa, E is the exponent, and b is a bias.

10. The processor of claim 9 , wherein at least some of the plurality of different variants of the floating point number format have different bias values from one another.

11. The processor of claim 1 , wherein at least one of the floating point operations comprises at least one item selected from a list consisting of:
combining the respective data value with a value from another register, wherein the other register has a different size than a fixed length of the operand registers in the group; and
placing a result of the operation in a further register having a different size than the fixed length of the operand registers.

12. The processor of claim 1 , wherein the floating point logic is operable to apply a different one of the plurality of different variants of the floating point number format to the data values operated on by at least some different ones of the types of machine code instruction.

13. The processor of claim 12 , further comprising at least one control register for holding one or more programmable settings, wherein a selected one of the variants of the floating point number format is specified by at least one of the programmable settings as determined from the at least one control register;
wherein the variants of the floating point number format for the data values of the different types of machine code instruction are programmable via the settings in the at least one control register.

14. The processor of claim 1 , programmed to use one of the first and second data values to represent a weight of a neural network.

15. The processor of claim 14 , wherein said same floating point operation comprises:
combining the first and second data values held in the first and second operand registers with a value from a further register, wherein the further register has a different size than a fixed length of the operand registers in the group; and
wherein the system is programmed to use the value in the further register to represent an activation of a node of the neural network.

16. The processor of claim 1 , wherein the plurality of different variants consist of only a subset of possible combinat

Assignees

• Graphcore Ltd

Inventors

• Gore Mrudula
• Alexander Alan

Classifications

• G06F9/3013 Primary

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/30025

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F9/30105

  Register structure · CPC title

• G06N3/02

  Neural networks · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title