Processing of issued instructions

Patent metadata

Field	Value
Publication number	US-11966739-B2
Application number	US-202217941387-A
Country	US
Kind code	B2
Filing date	Sep 9, 2022
Priority date	Sep 9, 2022
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.

First claim

We claim:

1. An apparatus comprising:
a register file comprising a plurality of data registers; and
frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item,
wherein:
the processing circuitry is responsive to a first encoding of the issued instruction specifying a data register of the plurality of data registers, to at least one of:
read the input data item for the processing operation from the data register; and
write the output data item generated in the processing operation to the data register; and

the processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and at least one of:
perform a dequeue operation to dequeue the input data item for the processing operation from the queue; and
perform an enqueue operation to enqueue the output data item generated in the processing operation to the queue.

2. The apparatus of claim 1 , wherein the frontend circuitry is arranged to store a plurality of instructions and is configured to perform a comparison operation to compare an execution state of the processing circuitry to a plurality of trigger conditions each associated with an instruction of the plurality of instructions, and the frontend circuitry is responsive to the comparison indicating a match between one of the plurality of trigger conditions and the execution state to issue the instruction associated with that trigger condition as the issued instruction.

3. The apparatus of claim 2 , wherein the control circuitry is configured to update the execution state based on a current state of at least one buffer meeting a predetermined condition.

4. The apparatus of claim 3 , wherein the predetermined condition is at least one of a buffer full condition and a buffer empty condition.

5. The apparatus of claim 2 , wherein for at least one encoding of the trigger condition, the trigger condition is dependent on a current state of the at least one buffer.

6. The apparatus of claim 1 , wherein:
the buffer-region is one of a plurality of buffer-regions each for storing a corresponding queue of data items;
the frontend circuitry is responsive to a further encoding of the issued instruction to control the processing circuitry to process the input data item and a further input data item to generate the output data item; and
the processing circuitry is responsive to the further encoding of the issued instruction to perform a further dequeue operation to dequeue the further input data item from the corresponding queue of a second buffer-region of the plurality of buffer-regions.

7. The apparatus of claim 6 , wherein:
the buffer-region and the second buffer-region are a same buffer region; and
the dequeue operation and the further dequeue operation comprise dequeuing the input data item and the further input data item from the queue.

8. The apparatus of claim 1 , wherein:
the second encoding of the issued instruction comprises an opcode and a register specifier field specifying one of a set of one or more buffer enqueue/dequeue registers; and
the first encoding of the issued instruction comprises the opcode and the register specifier field specifying the data register.

9. The apparatus of claim 1 , wherein the first encoding of the issued instruction and the second encoding of the issued instruction correspond to different opcodes.

10. The apparatus of claim 1 , comprising configuration storage to store configuration data comprising a head pointer identifying an enqueue location in the register file from which to perform the enqueue operation and a tail pointer identifying a dequeue location in the register file from which to perform the dequeue operation.

11. The apparatus of claim 10 , wherein the enqueue operation comprises writing the output data item to the enqueue location and updating the head pointer to indicate a next enqueue location in the register file and the dequeue operation comprises reading the input data item from the dequeue location and updating the tail pointer to indicate a next dequeue location in the register file.

12. The apparatus of claim 10 , wherein the processing circuitry is responsive to a third encoding of the issued instruction specifying the buffer-region of the register file to perform a no-dequeue read operation comprising reading the input data item from the dequeue location and retaining a current value of the tail pointer.

13. The apparatus of claim 10 , wherein the configuration data comprises information identifying the buffer-region.

14. The apparatus of claim 10 , wherein the configuration storage is comprised in the register file.

15. The apparatus of claim 10 , wherein the frontend circuitry is responsive to an update configuration instruction identifying new configuration data, to update the configuration data to the new configuration data.

16. The apparatus of claim 1 , wherein the frontend circuitry is responsive to a buffer access instruction specifying an element of the buffer, to cause the processing circuitry to access a specified data item stored in the element of the buffer.

17. The apparatus of claim 1 , wherein the buffer-region of the register file overlaps the plurality of data registers.

18. The apparatus of claim 1 , wherein the buffer-region is a circular buffer region.

19. A method of operating an apparatus comprising a register file comprising a plurality of data registers, the method comprising:
controlling, in response to an issued instruction, processing circuitry to perform a processing operation to process an input data item to generate an output data item,
wherein
in response to a first encoding of the issued instruction specifying a data register of the plurality of data registers, the controlling comprises at least one of:
reading the input data item for the processing operation from the data register; and
writing the output data item generated in the processing operation to the data register; and

in response to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, the controlling comprises controlling the processing circuitry to perform the processing operation and at least one of:
performing a dequeue operation to dequeue the input data item for the processing operation from the queue; and
performing an enqueue operation to enqueue the output data item generated in the processing operation to the queue.

20. A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:
a register file comprising a plurality of data registers; and
frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item,
wherein:
the processing circuitry is responsive to a first encoding of the issued instruction specifying a data register of the plurality of data registers, to at least one of:
read the input data item for the processing operation from the data register; and
write the output data item generated in the processing operation to the data register; and

the processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perf

Assignees

• Advanced Risc Mach Ltd

Inventors

• Walker Matthew James
• Eyole Mbou
• Gabrielli Giacomo
• VENU Balaji

Classifications

• G06F9/30123 Primary

  according to context, e.g. thread buffers · CPC title

• G06F9/30138

  Extension of register space, e.g. register cache · CPC title

• G06F9/3824 Primary

  Operand accessing · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/30098

  Register arrangements · CPC title