Method and system for comprehensively evaluating reliability of multi-chip parallel IGBT module

Patent metadata

Field	Value
Publication number	US-11966683-B2
Application number	US-202117503396-A
Country	US
Kind code	B2
Filing date	Oct 18, 2021
Priority date	Jan 6, 2021
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

A method and a system for comprehensively evaluating reliability of a multi-chip parallel IGBT module are provided. The method includes: establishing a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, performing a chip fatigue failure test, and selecting a gate-emitter voltage as a failure characteristic quantity; establishing a transconductance reliability model of the multi-chip parallel IGBT module, performing a bonding wire shedding failure test, and selecting a transmission characteristic curve of the module as a failure characteristic quantity; using a Pearson correlation coefficient to characterize a degree of health of the IGBT module, and respectively calculating degrees of health PPMCC C and PPMCC B in different degrees of chip fatigue and bonding wire shedding failure states; and comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to PPMCC C and PPMCC B .

First claim

What is claimed is:

1. A method for comprehensively evaluating reliability of a multi-chip parallel insulated gate bipolar transistor (IGBT) module, comprising:
Step (1) of establishing a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, implementing a chip fatigue failure test based on the gate-emitter voltage reliability model, and selecting a gate-emitter voltage as a failure characteristic quantity;
Step (2) of establishing a transconductance reliability model of the multi-chip parallel IGBT module, implementing a bonding wire shedding failure test based on the transconductance reliability model, and selecting a transmission characteristic curve of the module as a failure characteristic quantity;
Step (3) of defining a degree of health of the IGBT module, using a Pearson correlation coefficient to characterize the degree of health, and calculating a linear correlation PPMCC C in different degrees of chip fatigue failure states and a linear correlation PPMCC B in different degrees of bonding wire shedding failure states; and
Step (4) of comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to PPMCC C and PPMCC B .

2. The method for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 1 , wherein Step (3) specifically comprises:
Step (3.1) of adopting the degree of health to characterize the reliability of the IGBT module, wherein when the module has no chip fatigue failure and no bonding wire shedding failure, the degree of health is maximum, when the IGBT module is in a healthy initial state without chip fatigue failure, a gate-emitter voltage eigenvector is {right arrow over (x)}, and when i chips fail in the IGBT module, a gate-emitter voltage eigenvector is {right arrow over (y)} i ; and when the IGBT module is in the healthy initial state without bonding wire shedding failure, a transmission characteristic curve eigenvector of the IGBT module is {right arrow over (m)}, and when p bonding wires shed in the IGBT module, a transmission characteristic curve eigenvector of the IGBT module is n p ;
Step (3.2) of obtaining the linear correlation PPMCC C between the gate-emitter voltage in a chip fatigue failure state and a healthy state based on the gate-emitter voltage eigenvector {right arrow over (x)} and the gate-emitter voltage eigenvector {right arrow over (y)} i , wherein the greater the PPMCC C , the higher the correlation between the two, the higher the degree of health of chips, and the stronger the reliability; and
Step (3.3) of obtaining the linear correlation PPMCC B between the transmission characteristic curve in a bonding wire shedding failure state and the healthy state based on the transmission characteristic curve eigenvector {right arrow over (m)} of the IGBT module and the transmission characteristic curve eigenvector n p of the IGBT module, wherein the greater the PPMCC B , the greater the correlation between the two, the higher the degree of health of bonding wires, and the higher the reliability of the module.

3. The method for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 2 , wherein the linear correlation PPMCC C =r({right arrow over (x)}, {right arrow over (y)} l ) between the gate-emitter voltage in the chip fatigue failure state and the healthy state is obtained from

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Assignees

• Univ Wuhan

Inventors

• He Yigang
• Wang Chenyuan
• Li Lie
• Du Bolun
• Zhang Hui
• He Liulu

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2111/10

  Numerical modelling · CPC title

• G06F2119/02

  Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA] · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2119/04

  Ageing analysis or optimisation against ageing · CPC title