Semiconductor chip providing on-chip self-testing of an ana-log-to-digital converter implemented in the semiconductor chip

Patent metadata

Field	Value
Publication number	US-11962320-B2
Application number	US-201917753917-A
Country	US
Kind code	B2
Filing date	Dec 23, 2019
Priority date	Dec 23, 2019
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

First claim

What is claimed is:

1. A semiconductor chip providing on-chip self-testing of an analog-to-digital converter implemented in the semiconductor chip, the semiconductor chip comprising:
the analog-to-digital converter;
a digital-to-analog converter configured to generate and supply a radio frequency test signal to the analog-to-digital converter via a supply path, wherein the analog-to-digital converter is configured to generate digital output data based on the radio frequency test signal;
a reference data generation circuit configured to generate digital reference data; and
a comparator circuit configured to compare the digital output data to the digital reference data in order to determine error data.

2. The semiconductor chip of claim 1 , wherein the error data is indicative of a quantization error of the analog-to-digital converter.

3. The semiconductor chip of claim 1 , wherein the digital-to-analog converter is a 1-bit digital-to-analog converter with a mixed-signal finite impulse response filter output stage.

4. The semiconductor chip of claim 1 , wherein the radio frequency test signal is a sinusoidal signal.

5. The semiconductor chip of claim 1 , further comprising:
a gain correction circuit configured to modify, based on gain correction data, the digital output data in order to compensate for a signal gain of the supply path,
wherein the gain correction circuit is coupled between the analog-to-digital converter and the comparator circuit.

6. The semiconductor chip of claim 5 , wherein the gain correction circuit is further configured to determine the gain correction data based on the error data and the digital output data.

7. The semiconductor chip of claim 6 , wherein the gain correction circuit is configured to determine the gain correction by:
combining a sample of the error data and a sample of the digital output data in order to obtain a first sample;
bit-shifting the first sample; and
obtaining a sample of the gain correction data by combining the bit-shifted first sample with a preceding sample of the gain correction data.

8. The semiconductor chip of claim 7 , wherein the gain correction circuit is configured to combine the sample of the error data and the sample of the digital output data by combining the sample of the error data and the signum function of the sample of the digital output data.

9. The semiconductor chip of claim 7 , wherein the gain correction circuit is configured to determine the gain correction data by further delaying the sample of the gain correction data.

10. The semiconductor chip of claim 1 , wherein the reference data generation circuit is configured to generate the digital reference data taking into account a signal propagation delay over the supply path.

11. The semiconductor chip of claim 1 , wherein the reference data generation circuit comprises a numerically controlled oscillator configured to generate the digital reference data based on frequency control data.

12. The semiconductor chip of claim 11 , wherein the numerically controlled oscillator is further configured to generate the digital reference data based on signal propagation delay data indicative of a signal propagation delay over the supply path.

13. The semiconductor chip of claim 12 , wherein the numerically controlled oscillator comprises:
a first input node for the frequency control data;
a second input for the signal propagation delay data;
a first combiner circuit configured to combine a sample of the frequency control data with a phase accumulation sample in order to generate an updated phase accumulation sample, wherein the phase accumulation sample is an accumulation of preceding samples of the frequency control data,
a delay circuit configured to delay the updated phase accumulation sample;
a second combiner circuit configured to combine a sample of the signal propagation delay data and the delayed updated phase accumulation sample in order to generate a control sample; and
a CORDIC circuit configured to generate the digital reference data based on the control sample.

14. The semiconductor chip of claim 13 , wherein the numerically controlled oscillator further comprises a quantizer circuit coupled between the second combiner circuit and the CORDIC circuit and configured to quantize the control sample.

15. The semiconductor chip of claim 13 , wherein the CORDIC circuit is further configured to generate a phase shifted replica of the digital reference data.

16. The semiconductor chip of claim 12 , wherein the reference data generation circuit comprises loop circuitry configured to generate the signal propagation delay data based on the error data and a phase shifted replica of the digital reference data, wherein the phase shifted replica of the digital reference data is output by the numerically controlled oscillator.

17. The semiconductor chip of claim 16 , wherein the loop circuitry is configured to generate the signal propagation delay data by:
combining a sample of the error data and a sample of the phase shifted replica of the digital reference data in order to obtain a second sample;
bit-shifting the second sample; and
obtaining a sample of the signal propagation delay data by combining the bit-shifted second sample with a preceding sample of the signal propagation delay data.

18. The semiconductor chip of claim 17 , wherein the loop circuitry is configured to combine the sample of the error data and the sample of the phase shifted replica of the digital reference data by combining the sample of the error data and the signum function of the sample of the phase shifted replica of the digital reference data.

19. The semiconductor chip of claim 17 , wherein the loop circuitry is configured to generate the signal propagation delay data by further delaying the sample of the signal propagation delay data.

20. The semiconductor chip of claim 16 , wherein the phase shifted replica of the digital reference data is phase-shifted by 90° with respect to the digital reference data.

21. The semiconductor chip of claim 1 , wherein the digital-to-analog converter is configured to generate the radio frequency test signal based on digital control data, and wherein the semiconductor chip further comprises a numerically controlled oscillator configured to generate the digital control data.

22. A receiver, comprising:
a semiconductor chip according to claim 1 ; and
analog circuitry configured to receive a radio frequency receive signal from an antenna element, and to supply the radio frequency receive signal for digitization to the analog-to-digital converter.

23. A base station, comprising:
a receiver according to claim 22 ;
and a transmitter configured to generate a radio frequency transmit signal.

24. A mobile device, comprising:
a receiver according to claim 22 ;
and a transmitter configured to generate a radio frequency transmit signal.

25. A method for on-chip self-testing of an analog-to-digital converter, comprising:
generating a radio frequency test signal using a digital-to-analog converter implemented in the same semiconductor chip as the analog-to-digital converter;
supplying the radio frequency test signal to the analog-to-digital converter via a supply path;
generating digital output data based on the radio frequency test signal by the analog-to-digital converter;
generating digital reference data using a reference data generation circuit implemented in the semicon

Assignees

• Intel Corp

Inventors

• Azadet Kameran
• Clara Martin
• Gruber Daniel
• Molina Albert
• Shin Hundo

Classifications

• H03M1/1071 Primary

  Measuring or testing · CPC title

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/3187

  Built-in tests · CPC title

• G01R31/26

  Testing of individual semiconductor devices (testing of photovoltaic devices H02S50/10; testing or measuring during manufacture or treatment {H10P74/00}) · CPC title

• H03M1/0854

  of quantisation noise · CPC title