Sub-sampling phase locked loop with compensated loop bandwidth and integrated circuit including the same

Patent metadata

Field	Value
Publication number	US-11962311-B2
Application number	US-202217865811-A
Country	US
Kind code	B2
Filing date	Jul 15, 2022
Priority date	Oct 20, 2021
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.

First claim

What is claimed is:

1. A sub-sampling phase locked loop (PLL) comprising:
a slope generating and sampling circuit configured to generate a sampling voltage based on a reference clock signal and an output clock signal;
a first transconductance circuit configured to generate a first output control voltage based on the sampling voltage, a reference voltage, and a control current;
a second transconductance circuit configured to generate a second output control voltage based on the sampling voltage, the reference voltage, and the control current;
a constant transconductance bias circuit including a switched capacitor resistor (SCR), the constant transconductance bias circuit configured to generate the control current;
a loop filter connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit; and
a voltage controlled oscillator (VCO) configured to generate the output clock signal based on the first output control voltage and the second output control voltage,
wherein the constant transconductance bias circuit further includes
a first circuit connected between a power supply voltage and a ground voltage, and
a second circuit connected to the power supply voltage and the first circuit, and configured to output the control current, and

wherein the switched capacitor resistor is connected between the first circuit and the ground voltage and the switched capacitor resistor is configured to operate based on a first phase signal and a second phase signal.

2. The sub-sampling phase locked loop of claim 1 , wherein the switched capacitor resistor includes:
a first switch connected between a first node and a second node, the first switch configured to be turned on and off based on the first phase signal, the first node being connected to the first circuit;
a first capacitor connected between the second node and the ground voltage; and
a second switch connected in parallel with the first capacitor between the second node and the ground voltage, the second switch configured to be turned on and off based on the second phase signal.

3. The sub-sampling phase locked loop of claim 2 , wherein a current level of the control current generated by the constant transconductance bias circuit is proportional to a capacitance of the first capacitor.

4. The sub-sampling phase locked loop of claim 2 , wherein an active duration of the first phase signal and an active duration of the second phase signal do not overlap.

5. The sub-sampling phase locked loop of claim 2 , wherein
the first circuit includes:
a first transistor and a second transistor connected in series between the power supply voltage and the ground voltage; and
a third transistor and a fourth transistor connected in series between the power supply voltage and the first node, and

a gate electrode of the first transistor and a gate electrode of the third transistor are connected to each other, and a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to each other.

6. The sub-sampling phase locked loop of claim 5 , wherein
the second circuit includes a fifth transistor connected between the power supply voltage and a third node, the third node outputting the control current, and
a gate electrode of the fifth transistor is connected to the gate electrode of the first transistor and the gate electrode of the third transistor.

7. The sub-sampling phase locked loop of claim 2 , wherein the loop filter includes:
a first resistor connected between the output terminal of the first transconductance circuit and the ground voltage; and
a second capacitor connected between the output terminal of the second transconductance circuit and the ground voltage.

8. The sub-sampling phase locked loop of claim 7 , wherein a voltage level of the first output control voltage generated by the first transconductance circuit is proportional to a resistance of the first resistor, and is proportional to a capacitance of the first capacitor.

9. The sub-sampling phase locked loop of claim 1 , wherein
a proportional path of the sub-sampling phase locked loop is formed by the first transconductance circuit, and
an integral path of the sub-sampling phase locked loop is formed by the second transconductance circuit.

10. The sub-sampling phase locked loop of claim 9 , wherein a loop bandwidth of the sub-sampling phase locked loop is proportional to a gain of the proportional path.

11. The sub-sampling phase locked loop of claim 9 , wherein
the first transconductance circuit includes a first input terminal, and a second input terminal, the first input terminal receiving the sampling voltage, the second input terminal receiving the reference voltage, and
the second transconductance circuit includes a third input terminal and a fourth input terminal, the third input terminal receiving the reference voltage, the fourth input terminal receiving the sampling voltage.

12. The sub-sampling phase locked loop of claim 9 , wherein the first transconductance circuit and the second transconductance circuit have a same structure.

13. The sub-sampling phase locked loop of claim 9 , wherein the first transconductance circuit and the second transconductance circuit have different structures.

14. The sub-sampling phase locked loop of claim 1 , wherein the slope generating and sampling circuit includes:
a first circuit connected between a power supply voltage and a ground voltage, the first circuit configured to operate based on the output clock signal; and
a second circuit connected to the first circuit and the ground voltage, the second circuit configured to operate based on the reference clock signal and configured to output the sampling voltage.

15. The sub-sampling phase locked loop of claim 14 , wherein
the first circuit includes: a first transistor, a first resistor, and a second transistor connected in series between the power supply voltage and the ground voltage, and
a gate electrode of the first transistor and a gate electrode of the second transistor are configured to receive the output clock signal.

16. The sub-sampling phase locked loop of claim 15 , wherein the second circuit includes:
a first switch connected between the first resistor and a first node, the first switch configured to be turned on and off based on the reference clock signal;
a second switch connected between the first node and a second node, the second switch configured to be turned on and off based on an inverted reference clock signal, in the inverted reference clock signal the reference clock signal is inverted, the second node outputting the sampling voltage;
a first capacitor connected between the first node and the ground voltage; and
a second capacitor connected between the second node and the ground voltage.

17. The sub-sampling phase locked loop of claim 16 , wherein the second circuit is configured such that a slope of the sampling voltage is inversely proportional to a resistance of the first resistor, and the slope of the sampling voltage is inversely proportional to capacitances of the first and second capacitors.

18. An integrated circuit comprising:
a sub-sampling phase locked loop (PLL) configured to generate an output clock signal based on a reference clock signal; and
an internal circuit configured to operate based on the output clock signal,
wherein the sub-sampling phase locked loop includes
a slope generating and sampling circuit configured to generate a sampling voltage based on the reference clock signal

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Gyusik
• Kim Seungjin
• Oh Seunghyun

Classifications

• H03L7/091 Primary

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title