Array substrate and mother-board for array substrates

Patent metadata

Field	Value
Publication number	US-11961846-B2
Application number	US-202117358419-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	May 28, 2019
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

The application discloses an array substrate and a mother-board for array substrates. The array substrate includes a display area and a non-display area on a periphery of the display area. The non-display area is provided with an interface area. The array substrate includes: multiple signal lines extending in the display area and leading to the non-display area; multiple pads located in the interface Area, and each of the multiple pads is connected to a corresponding one of the multiple signal lines; and a short-circuiting component located in the non-display area, wherein the short-circuiting component is connected with the multiple pads, the multiple signal lines connected with the pads are short-circuited, and the short-circuiting component includes a patterned first metal structure. The array substrate according to embodiments of the present application can avoid problems caused by static electricity, such as, electrostatic damage or product defects.

First claim

What is claimed is:

1. An array substrate having a display area and a non-display area on a periphery of the display area, wherein the non-display area is provided with an interface area, and the array substrate comprises:
a plurality of signal lines, extending in the display area and leading out to the non-display area;
a plurality of pads located in the interface area, wherein each of the plurality of pads is connected with a corresponding one of the plurality of signal lines; and
a short-circuiting component located in the non-display area, wherein the short-circuiting component is connected with the plurality of pads, the plurality of signal lines connected with the plurality of pads are short-circuited, the short-circuiting component includes a semiconductor structure and a first metal structure, and an orthographic projection of the semiconductor structure in a thickness direction of the array substrate coincides with an orthographic projection of the first metal structure in the thickness direction of the array substrate, and the semiconductor structure and the first metal structure have the same structure in a plane dimension perpendicular to the thickness direction of the array substrate.

2. The array substrate of claim 1 , further comprising:
a plurality of pixel circuits arranged in the display area, wherein each of the plurality of pixel circuits is connected with at least one of the plurality of signal lines, the plurality of pixel circuits comprise a gate conductor, and the gate conductor is made of a material same as that of the first metal structure.

3. The array substrate of claim 2 , wherein the first metal structure and the gate conductor are arranged in a same layer.

4. The array substrate of claim 1 , wherein each of the plurality of pads comprises a first pad unit and a second pad unit arranged with an interval in a first direction, the first pad unit is connected with a corresponding one of the plurality of signal lines, the second pad unit is connected with the short-circuiting component, the first pad unit and the second pad unit are both connected to an interconnection block of the short-circuiting component through via holes, and the first pad unit and the second pad unit are electrically connected.

5. The array substrate of claim 4 , further comprising:
a plurality of pixel circuits arranged in the display area, wherein each of the plurality of pixel circuits is connected with at least one of the plurality of signal lines, the plurality of pixel circuits comprise an active layer, and the active layer is made of a material same as that of the interconnection block.

6. The array substrate of claim 5 , wherein the interconnection block and the active layer are arranged in a same layer.

7. The array substrate of claim 1 , wherein an insulating layer is arranged between the first metal structure and the semiconductor structure.

8. The array substrate of claim 1 , further comprising:
a plurality of pixel circuits arranged in the display area, wherein each of the plurality of pixel circuits is connected with at least one of the plurality of signal lines, the plurality of pixel circuits comprise an active layer, and the active layer is made of a material same as that of the semiconductor structure.

9. The array substrate of claim 8 , wherein the semiconductor structure and the active layer are arranged in a same layer.

10. The array substrate of claim 1 , wherein the short-circuiting component further comprises:
a short-circuiting bar; and
a plurality of connection lines, wherein each of the plurality of pads is connected with the short-circuiting bar through a corresponding one of the plurality of connection lines;
and the short-circuiting component is connected to a stable voltage source.

11. The array substrate of claim 10 , further comprising:
a protection layer covering the short-circuiting component.

12. The array substrate of claim 11 , wherein a channel is provided on the protection layer, the channel penetrates from a surface of the protection layer to the first metal structure, and the channel is arranged to be intersected with the plurality of connection lines.

13. The array substrate of claim 1 , further comprising:
a substrate located in the non-display area, wherein the semiconductor structure is located on the substrate and the first metal structure is located on the semiconductor structure.

14. A motherboard comprising a plurality of array substrates of arranged in an array, wherein each of the plurality of array substrates comprises a display area and a non-display area on a periphery of the display area, the non-display area is provided with an interface area, and the plurality of array substrates comprises:
a plurality of signal lines, extending in the display area and leading out to the non-display area;
a plurality of pads located in the interface area, wherein each of the plurality of pads is connected with a corresponding one of the plurality of signal lines; and
a short-circuiting component located in the non-display area, wherein the short-circuiting component is connected with the plurality of pads, the plurality of signal lines connected with the plurality of pads are short-circuited, the short-circuiting component includes a semiconductor structure and a first metal structure, and an orthographic projection of the semiconductor structure in a thickness direction of the array substrate coincides with an orthographic projection of the first metal structure in the thickness direction of the array substrate, and the semiconductor structure and the first metal structure have the same structure in a plane dimension perpendicular to the thickness direction of the array substrate.

15. The motherboard of claim 14 , wherein the plurality of array substrates are arranged into a plurality of rows, and each of the plurality of rows accommodates multiple array substrates of the plurality of array substrates, and the motherboard further comprises:
a short-circuiting interconnection component comprising a first interconnection unit for connecting the multiple array substrates in a same row in series, and a second interconnection unit for connecting at least two rows of the plurality of rows of the plurality of array substrates in parallel.

16. The motherboard of claim 15 , wherein the short-circuiting interconnection component further comprises:
a second metal structure configured to connect to the first metal structure through a via hole.

17. The motherboard of claim 14 , wherein the plurality of array substrates comprises:
a plurality of pixel circuits arranged in the display area, wherein each of the plurality of pixel circuits is connected with at least one of the plurality of signal lines, the plurality of pixel circuits comprise a gate conductor, the gate conductor is made of a material same as that of the first metal structure, and the first metal structure and the gate conductor are arranged in a same layer.

18. The motherboard of claim 14 , wherein each of the plurality of pads comprises a first pad unit and a second pad unit arranged with an interval in a first direction, the first pad unit is connected with a corresponding one of the plurality of signal lines, the second pad unit is connected with the short-circuiting component, and the first pad unit and the second pad unit are both connected to an interconnection block of the short-circuiting component through via holes, the first pad unit and the second pad unit are electrically connected; the plurality of array substrates comprises
a plurality

Assignees

• Kunshan Govisionox Optoelectronics Co Ltd

Inventors

• Liu Quan
• Qin Xu
• Li Weilong
• Zhang Lu
• Hu Siming
• Han Zhenzhen

Classifications

• H10D86/443 Primary

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title