Semiconductor device having multiple electrostatic discharge (ESD) paths

Patent metadata

Field	Value
Publication number	US-11961834-B2
Application number	US-202217699471-A
Country	US
Kind code	B2
Filing date	Mar 21, 2022
Priority date	Sep 18, 2019
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first diode having a plurality of first doped straps that extend in a first direction and configured as a plurality of terminals coupled to a first voltage terminal; and
a second diode having a second doped strap that extends in the first direction and is separated from the plurality of first doped straps in a second direction different from the first direction, wherein the second diode further comprises a plurality of third doped straps that are coupled to a second voltage terminal having a higher voltage level than that of the first voltage terminal,
wherein the second doped strap is configured as a first terminal of the second diode to be coupled to an input/output (I/O) pad,
wherein the first diode and the second diode include a first semiconductor structure configured to operate as a first equivalent silicon controlled rectifier circuit between the I/O pad and the first voltage terminal.

2. The semiconductor device of claim 1 , further comprising:
a third diode having a plurality of fourth doped straps that are coupled to the first voltage terminal,
wherein the plurality of first doped straps and the plurality of fourth doped straps are arranged in a first well.

3. The semiconductor device of claim 1 , further comprising:
a shallow trench isolation interposed between the second doped strap and a first strap of the plurality of the first doped straps,
wherein the second doped strap is of a first conductivity type and the first strap of the plurality of the first doped straps is of a second conductivity type different from the first conductivity type.

4. The semiconductor device of claim 1 , wherein the plurality of first doped straps have a first group of the plurality of first doped straps and a second group of the plurality of first doped straps,
wherein the first group and the second group are arranged on opposite sides of the second diode.

5. The semiconductor device of claim 1 , further comprising:
a third diode coupled in series with the second diode between the first voltage terminal and the second voltage terminal, comprising:
a fourth doped strap of a first conductivity type arranged on a first side of the second diode and coupled to the I/O pad; and
a plurality of fifth doped straps of a second conductivity type, wherein the second doped strap is interposed between the fourth doped strap and the plurality of fifth doped straps,
wherein the plurality of fifth doped straps are coupled to the first voltage terminal.

6. The semiconductor device of claim 5 , wherein the first diode is arranged on a second side, opposite to the first side, of the second diode.

7. The semiconductor device of claim 1 , wherein
the plurality of third doped straps are of a first conductivity type, and the second doped strap is of a second conductivity type different from the first conductivity type.

8. The semiconductor device of claim 7 , wherein the second doped strap and the plurality of third doped straps are interposed between the plurality of first doped straps.

9. A semiconductor device, comprising:
a first diode, wherein a first terminal of the first diode is coupled to a first voltage terminal that is configured to receive a first supply voltage, wherein the first diode is configured to direct a first part of an electrostatic discharge (ESD) current flowing between an input/output (I/O) pad and the first voltage terminal;
a second diode, wherein a first terminal of the second diode, the I/O pad, and a second terminal of the first diode are coupled to each other, and a second terminal of the second diode is coupled to a second voltage terminal that is configured to receive a second supply voltage, wherein the second diode has a first doped region that corresponds to the first terminal of the second diode and extends in a first direction; and
a third diode, wherein first and second terminals of the third diode are coupled to the first voltage terminal,
wherein the second diode and the third diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

10. The semiconductor device of claim 9 , wherein the first semiconductor structure in the second diode and the third diode is configured to operate as an equivalent silicon controlled rectifier (SCR) circuit.

11. The semiconductor device of claim 9 , wherein the first semiconductor structure in the second diode and the third diode comprises:
a substrate;
a first well of a first type disposed on the substrate, wherein the first doped region is of a second type different from the first type and disposed in the first well;
a second doped region of the first type disposed in the first well and configured as the second terminal of the second diode;
a second well of the second type disposed on the substrate and adjacent to the first well;
a third doped region of the first type disposed in the second well and configured as the first terminal of the third diode; and
a fourth doped region of the second type disposed in the second well and configured as the second terminal of the third diode;
wherein the first doped region, the first well, the substrate, the second well, and the third doped region are configured to operate as an equivalent silicon controlled rectifier (SCR) circuit.

12. The semiconductor device of claim 11 , wherein the first semiconductor structure in the second diode and the third diode further comprises:
a plurality of fifth doped regions of the first type disposed in the first well and corresponding to the second terminal of the second diode, wherein the second doped region is disposed between the plurality of fifth doped regions and the first doped region.

13. The semiconductor device of claim 9 , wherein the first doped region is of a first type and disposed in a first well of a second type different from the first type;
wherein the first semiconductor structure in the second diode and the third diode comprises:
second and third doped regions of the second type that are disposed in second and third wells of the first type and corresponding to the first terminal of the third diode, wherein the first well is interposed between the second and third wells.

14. The semiconductor device of claim 13 , wherein the first semiconductor structure in the second diode and the third diode further comprises:
fourth and fifth doped regions of the second type that are disposed in the second and third wells and corresponding to the second terminal of the third diode.

15. The semiconductor device of claim 13 , wherein the first semiconductor structure in the second diode and the third diode further comprises:
a plurality of fourth doped regions of the second type disposed in the first well and corresponding to the second terminal of the second diode, wherein the plurality of fourth doped regions are arranged between the second and third doped regions.

16. A semiconductor device, comprising:
a first diode having at least one first doped strap and a second doped strap in a first well, wherein the at least one first doped strap is configured as at least one terminal coupled to a first voltage terminal and the second doped strap is coupled to an input/output (I/O) pad; and
a second diode having a third doped strap that is in a second well different from the first well and separated from the at least one first doped strap,
wherein the third doped strap is configured as a first terminal of the second diode to be coupled to a second voltage terminal,
wherein the f

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Po-Lin
• Chu Li-Wei
• Tsai Ming-Fu
• Lee Jam-Wem
• Su Yu-Ti

Classifications

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D84/615

  Combinations of vertical BJTs and one or more of resistors or capacitors · CPC title