Testing of on-chip analog-mixed signal circuits using on-chip memory

Patent metadata

Field	Value
Publication number	US-11961577-B2
Application number	US-202217810671-A
Country	US
Kind code	B2
Filing date	Jul 5, 2022
Priority date	Jul 5, 2022
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2 N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.

First claim

What is claimed is:

1. A method for on-chip testing of analog-to-digital converters (ADCs) in an integrated circuit, the ADCs including a first set of ADCs of a first ADC type and a second set of ADCs of a second ADC type, different from the first ADC type, the method comprising:
performing calibration of an N-bit differential digital-to-analog converter (DAC) used in performing the on-chip testing of the ADCs and storing a pair of calibration codes for each of 2 N possible DAC input codes for the DAC in an on-chip memory;
testing the first set of ADCs using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC; and
after the testing the first set of ADCs, testing the second set of ADCs using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, wherein M and N are positive integers and M is less than N, wherein during the testing of the second set of ADCs, the method further comprises overwriting a portion of the calibration codes stored in the on-chip memory.

2. The method of claim 1 , wherein, after performing the calibration, each addressable memory line of the on-chip memory stores multiple pairs of calibration codes.

3. The method of claim 2 , wherein, for each addressable memory line of the on-chip memory:
each of the multiple pairs of calibration codes corresponds to a DAC input code having a same upper portion of significant bits as a memory address of the addressable memory line.

4. The method of claim 3 , wherein, for each addressable memory line of the on-chip memory:
a pair of the multiple pairs of calibration codes is selectable by at least a least significant bit of the DAC input code corresponding to the pair of the multiple pairs of calibration codes.

5. The method of claim 1 , wherein the pair of calibration codes for each of the 2 N possible DAC input codes for the DAC in the on-chip memory includes a corresponding first calibration code for the DAC input code for use with a first input of the differential DAC during ADC testing and a corresponding second calibration code for the DAC input code for use with a second input of the differential DAC during ADC testing.

6. The method of claim 5 , wherein the corresponding first calibration code and the corresponding second calibration code for a first N-bit DAC input code of the 2 N possible DAC input codes is stored in a first memory line of the on-chip memory addressed by upper significant bits of the first DAC input code, wherein the first memory line is obtainable with a single read access to the on-chip memory.

7. The method of claim 6 , wherein the first memory line of the on-chip memory further stores the corresponding first calibration code and the corresponding second calibration code for a second N-bit DAC input code of the 2 N possible DAC input codes, wherein the first and second N-bit DAC input codes differ by only a least significant bit (LSB), wherein:
the corresponding first and second calibration codes for the first DAC input are indicated by a first value of the LSB, and
the corresponding first and second calibration codes for the second DAC input are indicated by a second value of the LSB.

8. The method of claim 1 , wherein the testing the first set of ADCs using the pairs of calibration codes stored in the on-chip memory and the full N-bit resolution of the DAC comprises:
generating a first DAC input code;
accessing a first address line of the on-chip memory addressed by N−1 upper significant bits of the first DAC input code, wherein the N−1 upper significant bits is capable of addressing any memory line of the on-chip memory;
providing a selected pair of calibration codes corresponding to the received first DAC input code from the first accessed address line, based on an LSB of the first input code, to calibrate the DAC during testing the first set of ADCs.

9. The method of claim 8 , wherein the testing the second set of ADCs using pairs of calibration codes corresponding to the reduced M-bit resolution of the DAC comprises:
generating a second DAC input code;
accessing a second address line of the on-chip memory addressed by N−1 upper significant bits of the second DAC input code, wherein the N−1 upper significant bits of the second DAC input code is capable of addressing only a first portion of memory locations of the on-chip memory; and
providing a selected pair of calibration codes corresponding to the received second DAC input code from predetermined byte locations of the second accessed line to calibrate the DAC during testing the second set of ADCs.

10. The method of claim 9 , wherein the testing the second set of ADCs using pairs of calibration codes corresponding to the reduced M-bit resolution of the DAC further comprises:
performing reads, writes, or both reads and write in a second portion of memory locations of the on-chip memory, mutually exclusive with the first portion, in which the first portion of memory locations and the second portion of memory locations together provide all memory locations of the on-chip memory, wherein performing writes in the second portion of memory locations overwrites calibration codes stored in an addressed memory line of the second portion of memory locations.

11. The method of claim 10 , wherein after performing testing of the first set of ADCs and the second set of ADCs, repeating the performing the calibration of the N-bit differential DAC to repeat storing the pairs of calibration codes for each of 2 N possible DAC input codes in the on-chip memory prior to subsequently re-testing the first set of ADCs.

12. The method of claim 1 , wherein the first set of ADCs comprises one or more sigma-delta ADCs (SDADCs), and the second set of ADCs comprises one or more successive approximation register ADCs (SARADCs).

13. An integrated circuit including built-in self-test (BIST) circuitry which performs on-chip testing of analog-to-digital converters (ADCs), the ADCs including a first set of ADCs of a first ADC type and a second set of ADCs of a second ADC type, different from the first ADC type, the integrated circuit comprising:
on-chip memory;
an N-bit differential digital-to-analog converter (DAC) used in performing the on-chip testing of the ADCs;
calibration circuitry coupled to the N-bit differential DAC and configured to generate a pair of calibration codes corresponding to each possible N-bit DAC input code for the N-bit differential DAC;
a memory engine, coupled to the calibration circuitry and the on-chip memory, and configured to:
store each pair of calibration codes in a memory line of the on-chip memory addressed by upper significant bits of a corresponding N-bit DAC input code, wherein, after generating all pairs of calibration codes, each memory line includes multiple pairs of calibration codes; and
obtain a first pair of calibration codes from the on-chip memory for a received DAC input code by initiating a read to receive read data from an address line in the on-chip memory addressed by N−1 upper significant bits of the received DAC input code and using a least significant bit (LSB) of the received DAC input code to select the first pair of calibration codes from the received read data.

14. The integrated circuit of claim 13 , further comprising:
an ADC under test coupled to receive an output of the N-bit differential DAC, wherein the memory engine is configured to provide a corresponding pair of calibration codes from the on-chip memory, including a first calibration code for use with an n-input of the N-bit differential DAC during ADC testing and a second calibration code for use with a p-input of the

Assignees

• Nxp Usa Inc

Inventors

• Abhishek Kumar
• Jin Xiankun
• Lehmann Mark

Classifications

• G11C29/46 Primary

  Test trigger logic · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/109 Primary

  for DC performance, i.e. static testing (H03M1/1085 takes precedence) · CPC title