Method and system for optimizing data transfer from one memory to another memory

Patent metadata

Field	Value
Publication number	US-11960889-B2
Application number	US-202117914262-A
Country	US
Kind code	B2
Filing date	Mar 25, 2021
Priority date	Mar 25, 2020
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A method and system for moving data from a source memory to a destination memory by a processor is disclosed herein. The destination memory stores a sequence of instructions and the sequence of instructions comprises one or more load instructions and one or more store instructions. The processor initially moves the one or more store instructions from the destination memory to the source memory. The processor then executes the one or more load instructions from the destination memory. On executing the one or more load instructions, the data is loaded from the source memory to at least one register in the processor. The processor further initiates execution of the one or more store instructions stored in the source memory. On executing the one or more store instructions from the source memory, the processor stores the data from the at least one register to the destination memory.

First claim

The invention claimed is:

1. A method of moving data from a source memory to a destination memory by a processor comprising a plurality of registers, the destination memory storing a sequence of instructions, wherein the sequence of instructions comprises one or more load instructions and one or more store instructions, the method comprising:
moving the one or more store instructions from the destination memory to the source memory;
executing of the one or more load instructions from the destination memory;
loading the data from the source memory to at least one register in the processor, on executing the one or more load instructions;
initiating execution of the one or more store instructions stored in the source memory; and
storing the data from the at least one register to the destination memory on executing the one or more store instructions from the source memory.

2. The method as claimed in claim 1 , wherein initiating the execution of the one or more store instructions stored in the source memory is performed on executing a branch instruction subsequent to the one or more load instructions stored in the destination memory.

3. The method as claimed in claim 1 , wherein moving the one or more store instructions is performed on executing a set of data transfer instructions in the sequence of instructions.

4. The method as claimed in claim 1 , wherein moving the one or more store instructions from the destination memory to the source memory is performed by executing a set of preconfigured instructions before executing the sequence of instructions.

5. The method as claimed in claim 1 , wherein the method further comprises performing execution of the load instruction by:
fetching the load instruction from the destination memory in a first clock cycle, said load instruction identifying a memory address in the source memory of data to be loaded;
fetching a subsequent load instruction from the destination memory in a second clock cycle; and
loading the data from the memory address in the source memory to a register in the plurality of registers in the second clock cycle.

6. The method as claimed in claim 1 , wherein the method further comprises performing execution of the store instruction by:
fetching the store instruction from the source memory in a first clock cycle, said store instruction identifying a memory address in the destination memory for storing the data;
fetching a subsequent store instruction from the source memory in a second clock cycle; and
storing the data from the register in the plurality of registers to the destination memory in the second cycle.

7. The method as claimed in claim 1 , wherein the one or more load instructions and the one or more store instructions are executed in a loop for moving the data from the source memory to the destination memory.

8. The method as claimed in claim 1 , wherein the one or more store instructions are stored among the sequence of instructions or as data in the destination memory.

9. The method as claimed in claim 1 , wherein the sequence of instructions and the data is stored as machine code.

10. The method as claimed in claim 1 , the method further comprises generating the sequence of instructions by converting an assembly code or source code written by a user.

11. A computer system configured for moving data, the system comprising:
a source memory configured to store data;
a destination memory configured to store sequence of instructions comprising one or more load instructions and one or more store instructions; and
a processor, coupled to the source memory and the destination memory, configured to execute the sequence of instructions, wherein the processor is configured to:
move the one or more store instructions from the destination memory to the source memory;
executing the one or more load instructions from the destination memory;
loading the data from the source memory to at least one register in the processor, on executing the one or more load instructions;
initiating execution of the one or more store instructions stored in the source memory; and
storing the data from the at least one register to the destination memory on executing the one or more store instructions from the source memory.

12. The system as claimed in claim 11 , wherein the processor moves the one or more store instructions to the source memory on executing a set of data transfer instructions among the sequence of instructions.

13. The system as claimed in claim 11 , wherein the processor moves the one or more store instructions from the destination memory to the source memory on executing a set of preconfigured instructions before executing the sequence of instructions.

14. The system as claimed in claim 11 , wherein the processor executes the one or more store instructions from the source memory on executing a branch instruction among the sequence of instructions.

15. The system as claimed in claim 11 , wherein the destination memory is configured to store sequence of instructions in a stack memory.

16. The system as claimed in claim 11 , wherein the processor is coupled to the source memory and the destination memory through an instruction path and a data path.

17. The system as claimed in claim 16 , wherein the processor fetches the instructions from the source memory and the destination memory through the instruction path.

18. The system as claimed in claim 16 , wherein the processor accesses the data from the source memory and move the data to the destination memory through the data path.

19. A non-transitory computer readable storage medium having encoded thereon computer readable code configured to cause the method of claim 1 to be performed when the code is run.

Assignees

• Nordic Semiconductor Asa

Inventors

• Smith Chris

Classifications

• G06F9/323

  for indirect branch instructions · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3004 Primary

  to perform operations on memory · CPC title

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title