Method and system for managing memory associated with a peripheral component interconnect express (PCIE) solid-state drive (SSD)

Patent metadata

Field	Value
Publication number	US-11960723-B2
Application number	US-202217867742-A
Country	US
Kind code	B2
Filing date	Jul 19, 2022
Priority date	May 27, 2022
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A method for managing a memory associated with PCIe SSD including: generating memory pools of equal size from a predefined size of contiguous physical memory, each of the memory pools manages a memory request of different size and is associated with a respective predefined size of memory request; dividing each of the memory pools into first set of memory pages, each having a size equal to maximum size among the predefined size of the memory request associated with the respective memory pool; dividing each of the first set of memory pages into second set of memory pages, each having a size equal to the predefined size of the memory request associated with respective memory pool; and managing the contiguous physical memory by allocating a memory page from the second set of memory pages fora memory request corresponding to the size of the second set of memory pages.

First claim

We claim:

1. A method for managing a memory associated with a Peripheral Component Interconnect Express (PCIe) Solid-State Drive (SSD), the method comprising:
generating, by a memory controller, a plurality of memory pools of equal size from a predefined size of contiguous physical memory associated with the PCIe SSD, wherein each of the plurality of memory pools manages a memory request of a different size, and wherein each of the plurality of memory pools is associated with a respective predefined size of memory request;
dividing, by the memory controller, each of the plurality of memory pools into a first set of memory pages, wherein each of the first set of memory pages has a size equal to a maximum size among the predefined size of the memory request associated with the respective memory pool;
dividing, lay the memory controller, each of the first set of memory pages into a second set of memory pages, wherein each of the second set of memory pages has a size equal to the predefined size of the memory request associated with respective memory pool; and
managing, by the memory controller, the contiguous physical memory associated with the PCIe SSD by allocating at least one memory page from the second set of memory pages for a memory request of a size corresponding to the size of the second set of memory pages.

2. The method as claimed in claim 1 , wherein the predefined size of the memory request for each of the plurality of memory pools is configured during compilation of one or more memory operations.

3. The method as claimed in claim 1 , wherein number of memory pools is configured during compilation of one or more memory operations based on the predefined size of the contiguous physical memory associated with the PCIe SSD.

4. The method as claimed in claim 1 , wherein allocating at least one memory page from the second set of memory pages comprises:
maintaining, by the memory controller, for each of the plurality of memory pools an allocation list and a free list associated with the first set of memory pages within each of the memory pools; and
shifting, by the memory controller, each of the first set of memory pages to the allocation list, upon allocating each of the second set of memory pages for the memory request.

5. The method as claimed in claim 4 , further comprising:
de-allocating, by the memory controller, the second set of memory pages associated with the memory request; and
shifting, by the memory controller, each of the first set of memory, pages to the free list, upon de-allocating the second set of memory pages associated with the memory request.

6. The method as claimed in claim 1 , further comprising:
identifying, by the memory controller, if each memory page from the second set of memory pages associated with the memory request is allocated;
obtaining, by the memory controller, a first set of memory pages from a memory pool associated with a memory request of a maximum size among the predefined sizes of memory requests; and
changing, by the memory controller, a size of second set of memory pages associated with the obtained first set of memory pages, wherein the size of the second set of memory pages associated with the obtained first set of memory pages is changed to the size of the second set of memory pages associated with the memory request.

7. A memory controller for managing a memory associated with a Peripheral Component Interconnect Express (PCIe) Solid-State Drive (SSD), comprising:
a processor configured to:
generate a plurality of memory pools of equal size from a predefined size of contiguous physical memory associated with the PCIe SSD, wherein each of the plurality of memory pools manages a memory request of a different size, and wherein each of the plurality of memory pools is associated with a respective predefined size of memory request;
divide each of the plurality of memory pools into a first set of memory pages, wherein each of the first set of memory pages is of a size equal to a maximum size among the predefined size of the memory request associated with the respective memory pool;
divide each of the first set of memory pages into a second set of memory pages, wherein each of the second set of memory pages is of a size equal to the predefined size of the memory request associated with respective memory pool; and
manage the contiguous physical memory associated with the PCIe SSD by allocating at least one memory page from the second set of memory pages for a memory request of a size corresponding to the size of the second set of memory pages.

8. The memory controller as claimed in claim 7 , wherein the predefined size of the memory request for each of the plurality of memory pools is configured during compilation of one or more memory operations.

9. The memory controller as claimed in claim 7 , wherein number of memory pools is configured during compilation of one or more memory operations based on the predefined size of the contiguous physical memory associated with the PCIe SSD.

10. The memory controller as claimed in claim 7 , wherein the processor allocates at least one memory page from the second set of memory pages by:
maintaining for each of the plurality of memory pools an allocation list and a free list associated with the first set of memory pages within each of the memory pools; and
shifting each of the first set of memory pages to the allocation list, upon allocating each of the second set of memory pages for the memory request.

11. The memory controller as claimed in claim 10 , wherein the processor:
de-allocates the second set of memory pages associated with the memory request; and
shifts each of the first set of memory pages to the free list, upon de-allocating the second set of memory pages associated with the memory request.

12. The memory controller as claimed in claim 7 , wherein the processor:
identities if each memory page from the second set of memory pages associated with the memory request is allocated;
obtains a first set of memory pages from a memory pool associated with a memory request of a maximum size among the predefined sizes of memory requests; and
changes a size of the second set of memory pages associated with the obtained first set of memory pages, wherein the size of the second set of memory pages associated with the obtained first set of memory pages is changed to the size of the second set of memory pages associated with the memory request.

13. A method for managing a memory associated with a Peripheral Component Interconnect Express (PCIe) Solid-State Drive (SSD), the method comprising:
generating a plurality of memory pools from a memory, wherein each of the memory pools has the same size;
dividing each of the memory pools into a first set of memory pages, wherein each memory page of the first set of memory pages has a size equal to a maximum size of a memory request for the all of the memory pools;
dividing each memory page of the first set of memory pages into a second set of memory pages, wherein each memory page of the second set of memory pages has a size equal to a size of a memory request associated with its respective memory pool; and
allocating at least one memory page from the second set of memory pages in response to a read/write operation having a size corresponding to the size of the second set of memory pages.

14. The method of claim 13 , wherein each of the memory pools is configured to manage a memory request of a different size.

15. The method of claim 13 , further comprising maintaining a free list and an allocation list for each of the memory pools, wherein the free list includes t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Reddy Krishna Kanth
• Sharma Dileep Kumar
• Kumar Neeraj

Classifications

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title