Multi-tile memory management mechanism

Patent metadata

Field	Value
Publication number	US-11960405-B2
Application number	US-202218148749-A
Country	US
Kind code	B2
Filing date	Dec 30, 2022
Priority date	Feb 26, 2020
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

First claim

What is claimed is:

1. A graphics processor for a multi-tile architecture, comprising:
a first graphics device having a local memory;
a second graphics device having a local memory; and
a processing resource that is configured to execute instructions to provide a single virtual allocation with a common virtual address range to interleave physical pages of a shared resource to local memory of the first and second graphics devices.

2. The graphics processor of claim 1 , wherein the single virtual allocation interleaves a first physical page to the local memory of the first graphics device and a second physical page to the local memory of the second graphics device.

3. The graphics processor of claim 1 , wherein the single virtual allocation interleaves a first subset of a physical page to the local memory of the first graphics device and a second subset of the physical page to the local memory of the second graphics device.

4. The graphics processor of claim 1 , wherein the first graphics device is communicatively coupled to the second graphics device.

5. The graphics processor of claim 1 , wherein the shared resource comprises a shared read/write buffer.

6. The graphics processor of claim 1 , further comprising:
a third graphics device having a local memory; and
a fourth graphics device having a local memory, wherein the processing resource is configured to execute instructions to form a first group including the first and third graphics devices for rendering frame N of a display device based on a node mask.

7. The graphics processor of claim 6 , wherein the processing resource is configured to execute instructions to form a second group including the second and the fourth graphics devices for rendering frame N+1 of the display device based on the node mask.

8. The graphics processor of claim 1 , wherein the first graphics device comprises a graphics tile of the multi-tile hierarchy.

9. The graphics processor of claim 1 , wherein the single virtual allocation with a common virtual address range to partition a render target on a per graphics device basis.

10. The graphics processor of claim 9 , wherein the single virtual allocation to allocate a first page of the render target to the local memory of the first graphics device and to allocate a second page of the render target to the local memory of the second graphics device.

11. A graphics processor for a multi-tile architecture, comprising:
a first graphics device having a local memory;
a second graphics device having a local memory; and
a processing resource that is configured to execute instruction to provide a heap with a common virtual address range for mapping virtual addresses of at least one resource into the heap and to interleave the at least one resource into the local memory of the first graphics device and the local memory of the second graphics device.

12. The graphics processor of claim 11 , wherein the processing resource is configured to execute instructions to interleave a first physical page to the local memory of the first graphics device and a second physical page to the local memory of the second graphics device.

13. The graphics processor of claim 11 , wherein the processing resource is configured to execute instructions to interleave a first subset of a physical page to the local memory of the first graphics device and a second subset of the physical page to the local memory of the second graphics device.

14. The graphics processor of claim 11 , wherein the at least one resource comprises a first resource including a texture and a second resource including a buffer.

15. A graphics processor, comprising:
a first graphics device having a local memory;
a second graphics device having a local memory;
a communication link to couple the first and second graphics devices; and
a memory management unit is configured to utilize a single virtual allocation with a common virtual address range to mirror a resource or to interleave physical pages of the resource to the local memory of the first and second graphics devices.

16. The graphics processor of claim 15 , wherein the memory management unit is further configured with a monitoring feature to monitor accesses to the communication link, the local memory of the first graphics device, the local memory of the second graphics device, to allocate data from resources to the first and second graphics devices, and to change allocation of the data to the first and second graphics devices based on the monitoring feature.

17. The graphics processor of claim 15 , wherein the single virtual allocation interleaves a first physical page to the local memory of the first graphics device and a second physical page to the local memory of the second graphics device.

Assignees

• Intel Corp

Inventors

• Waters Zack S
• Schluessler Travis
• Apodaca Michael
• Shah Ankur

Classifications

• G06F12/0882 Primary

  Page mode · CPC title

• G06F9/4411 Primary

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F11/3006

  where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50) · CPC title