Apparatus and method for pausing processor trace for efficient analysis

Patent metadata

Field	Value
Publication number	US-11960375-B2
Application number	US-202217834211-A
Country	US
Kind code	B2
Filing date	Jun 7, 2022
Priority date	Dec 29, 2017
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

First claim

What is claimed is:

1. A processor comprising:
a decoder to decode instrumented code; and
an execution circuitry to execute the instrumented code upon decoding, the execution is to:
detect a call to un-instrumented code during execution of the instrumented code,
execute and trace the un-instrumented code responsive to detecting the call to the un-instrumented code, and
return to execute the instrumented code and pause tracing upon the un-instrumented code being completed.

2. The processor of claim 1 , further comprising a trace register including one or more fields, the one or more fields indicating whether tracing is enabled.

3. The processor of claim 2 , wherein the decoder is to check the trace register to determine whether tracing has been enabled.

4. The processor of claim 1 , wherein calling the un-instrumented code comprises calling an instruction to resume tracing, followed by calling the un-instrumented code.

5. The processor of claim 1 , wherein calling the un-instrumented code comprises instrumenting an un-instrumented code call with an instruction prefix that causes trace resuming.

6. The processor of claim 1 , wherein the return to execute the instrumented code and pausing tracing comprises instrumenting a return call with an instruction prefix that causes tracing pause.

7. The processor of claim 1 , wherein the pausing tracing upon the un-instrumented code being completed comprises executing an instruction to pause tracing.

8. The processor of claim 7 , wherein the instruction to pause tracing comprises an operand value without which the pausing tracing is not performed.

9. The processor of claim 1 , wherein the pausing tracing upon the un-instrumented code being completed is based on a comparison of a stack point value with a threshold value.

10. The processor of claim 9 , wherein the threshold value is stored in a register.

11. A method comprising:
decoding, by a decoder of a processor, instrumented code; and
executing, by an execution circuitry of the processor, the instrumented code upon decoding, the execution is to:
detect a call to un-instrumented code during execution of the instrumented code,
execute and trace the un-instrumented code responsive to detecting the call to the un-instrumented code, and
return to execute the instrumented code and pause tracing upon the un-instrumented code being completed.

12. The method of claim 11 , wherein calling the un-instrumented code comprises calling an instruction to resume tracing, followed by calling the un-instrumented code.

13. The method of claim 11 , wherein calling the un-instrumented code comprises instrumenting an un-instrumented code call with an instruction prefix that causes trace resuming.

14. The method of claim 11 , wherein the return to execute the instrumented code and pausing tracing comprises instrumenting a return call with an instruction prefix that causes tracing pause.

15. The method of claim 11 , wherein the pausing tracing upon the un-instrumented code being completed comprises executing an instruction to pause tracing.

16. A non-transitory computer readable storage medium including instructions stored thereon which, when executed by a processor, cause the processor to perform:
decoding, by a decoder of the processor, instrumented code; and
executing, by an execution circuitry of the processor, the instrumented code upon decoding, the execution is to:
detect a call to un-instrumented code during execution of the instrumented code,
execute and trace the un-instrumented code responsive to detecting the call to the un-instrumented code, and
return to execute the instrumented code and pause tracing upon the un-instrumented code being completed.

17. The non-transitory computer readable storage medium of claim 16 , wherein the return to execute the instrumented code and pausing tracing comprises instrumenting a return call with an instruction prefix that causes tracing pause.

18. The non-transitory computer readable storage medium of claim 16 , wherein the pausing tracing upon the un-instrumented code being completed comprises executing an instruction to pause tracing.

19. The non-transitory computer readable storage medium of claim 18 , wherein the instruction to pause tracing comprises an operand value without which the pausing tracing is not performed.

20. The non-transitory computer readable storage medium of claim 16 , wherein the pausing tracing upon the un-instrumented code being completed is based on a comparison of a stack point value with a threshold value.

Assignees

• Intel Corp

Inventors

• Lemay Michael
• Strong Beeman

Classifications

• G06F11/3466 Primary

  Performance evaluation by tracing or monitoring · CPC title

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F21/56 Primary

  Computer malware detection or handling, e.g. anti-virus arrangements · CPC title

• G06F21/577

  Assessing vulnerabilities and evaluating computer system security · CPC title

• G06F2221/033

  Test or assess software · CPC title