Activity smoothener circuit controlling rates of change of localized processing activity in an integrated circuit (IC), and related methods

Patent metadata

Field	Value
Publication number	US-11960338-B2
Application number	US-202117182982-A
Country	US
Kind code	B2
Filing date	Feb 23, 2021
Priority date	Feb 23, 2021
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

An activity smoothener circuit is provided to control rates of change in processing activity to limit di/dt in activity areas of an IC to mitigate voltage droops or overshoots. Controlling the rate of change of activity prevents or reduces instances of a di/dt exceeding a programmed maximum that is based on physical limits of the IC and/or a package. In examples, the activity smoothener circuit includes a hierarchy of smoothening circuits controlling activity in areas down to individual circuit blocks (tiles) including execution circuits. An indication of a desired level of activity is provided to a parent smoothening circuit and the parent smoothening circuit responds with indications of actual activity allowed to occur. At each level of hierarchy, the activity smoothener circuit may use algorithms to generate indications of actual activity based on indications of desired activity and di/dt limits. Di/dt limits and current minimums and maximums are controlled.

First claim

What is claimed is:

1. An activity smoothener circuit in an integrated circuit (IC), the activity smoothener circuit comprising:
a plurality of circuit blocks (tiles) each comprising an execution circuit, each of the plurality of tiles configured to:
generate a first indication of desired activity of the tile, comprising a single-bit signal indicating a request for one of inactivity and activity in the execution circuit;
receive a first indication of actual activity for the tile, comprising a multi-bit signal representing an allowed level of activity; and
control task execution activity in the execution circuit of the tile according to the allowed level of activity indicated by the received first indication of actual activity for the tile;

a plurality of smoothening circuits, each corresponding to a cluster of the plurality of tiles, each of the plurality of smoothening circuits configured to:
receive the first indications of desired activity from each of the plurality of tiles;
generate a second indication of desired activity for the cluster, comprising a multi-bit signal indicating a requested level of activity in the cluster based on the first indications of desired activity in the plurality of tiles;
receive a second indication of actual activity for the cluster as a multi-bit signal representing an allowed level of activity for the cluster; and
generate the first indications of actual activity for each of the plurality of tiles based on the first indications of desired activity in the plurality of tiles, the second indication of actual activity in the cluster, and a first limit of a rate of change of current in each of the plurality of tiles of the IC; and

a top-level smoothening circuit coupled to the plurality of smoothening circuits, the top-level smoothening circuit configured to:
receive the second indications of desired activity from the plurality of clusters;
generate a third indication of desired activity for the IC based on the second indications of desired activity of the clusters, the third indication of desired activity comprising a multi-bit signal;
receive a third indication of actual activity for the IC comprising a multi-bit signal indicating a level of activity in the IC; and
generate the second indications of actual activity for the plurality of clusters based on the second indications of desired activity, the third indication of actual activity in the IC, and a second limit of a rate of change of current into the IC.

2. The activity smoothener circuit of claim 1 , wherein the execution circuit comprises a general-purpose processing circuit or an accelerator circuit.

3. The activity smoothener circuit of claim 1 , each of the plurality of tiles further comprising a work queue configured to receive one or more tasks to be executed by the execution circuit, wherein the first indication of desired activity indicates whether the work queue received a task to be executed.

4. The activity smoothener circuit of claim 1 , wherein the first indication of desired activity further indicates whether the execution circuit is currently executing a task.

5. The activity smoothener circuit of claim 1 , wherein in response to the first indication of actual activity in the tile, the execution circuit executes fake work that generates results which are discarded.

6. The activity smoothener circuit of claim 1 , wherein the first indications of actual activity in the tiles are accumulated and the execution circuit is configured to execute a task in response to an accumulation of the first indications of actual activity reaching a threshold.

7. The activity smoothener circuit of claim 1 , wherein the smoothening circuit configured to generate the second indication of desired activity in the cluster is further configured to generate a binary sum of the first indications of actual activity from the plurality of tiles.

8. The activity smoothener circuit of claim 1 , wherein the limit of the rate of change of current in each tile of the IC is programmed in the smoothening circuit and corresponds to a limit of a rate of change of activity in the plurality of tiles.

9. The activity smoothener circuit of claim 1 , wherein the smoothening circuit further comprises programmable registers configured to indicate at least one of:
an indication of a number of the plurality of tiles;
a floor (minimum) and a ceiling (maximum) for the second indication of actual activity for the cluster;
a limit of a rate of change of current (di/dt) increase; and
a limit of a rate of change of current decrease.

10. The activity smoothener circuit of claim 1 , wherein:
the third indication of desired activity comprises a signal output from the IC; and
the third indication of actual activity comprises a signal received from outside the IC.

11. The activity smoothener circuit of claim 1 , wherein:
the first indication of desired activity of the tile comprises an indication of power to be consumed by the tile during execution of at least one task received in a work queue.

12. The activity smoothener circuit of claim 1 , wherein each of the plurality of smoothening circuits further comprises:
a programmable register configured to indicate a maximum activity level based on a maximum power consumption level; and
a control circuit configured to stagger the first indications of actual activity to the plurality of tiles over time in response to the second indication of actual activity indicated an allowed level of activity exceeding the maximum activity level.

13. The activity smoothener circuit of claim 1 , wherein:
each of the plurality of smoothening circuits is further configured to provide first indications of actual activity to the plurality of tiles within a predetermined number of clock cycles following the first indications of desired activity; and
the predetermined number of clock cycles is programmed into the programmable registers.

14. The activity smoothener circuit of claim 1 , wherein each of the plurality of smoothening circuits further comprises:
a programmable register configured to indicate a minimum activity level based on a minimum power consumption level; and
a control circuit configured to increase the second indication of actual activity based on the minimum activity level indicated in the programmable register.

15. An integrated circuit (IC) comprising an activity smoothener circuit comprising:
a plurality of cluster smoothening circuits each corresponding to a cluster and each configured to:
receive a plurality of first indications of desired activity for each of a plurality of circuit blocks (tiles) that each comprise an execution circuit, wherein a first indication is generated in each of the tiles indicting a request for one of inactivity and activity in the execution circuit;
generate a second indication of desired activity for the cluster comprising a multi-bit signal indicating a requested level of activity in the cluster based on the plurality of first indications of desired activity;
receive a second indication of actual activity for the cluster as a multi-bit signal representing an allowed level of activity; and
generate a first indication of actual activity for each of the plurality of tiles based on the plurality of first indications of desired activity in the plurality of tiles, the second indication of actual activity in the cluster, and a first limit of a rate of change of current in each of the plurality of tiles; and

a node smoothening circuit configured to:
receive from each of the plurality of cluster smoothening circuits, the second indication of desired activity;
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Assignees

• Microsoft Technology Licensing Llc

Inventors

• Rapaka Smitha L
• Gladding Derek E
• Xu Xiaoling

Classifications

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/305

  in the event of power-supply fluctuations · CPC title

• G06F9/4893

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/329

  by task scheduling · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title