Circuit check method and electronic apparatus

Patent metadata

Field	Value
Publication number	US-11959956-B2
Application number	US-202017125034-A
Country	US
Kind code	B2
Filing date	Dec 17, 2020
Priority date	Dec 18, 2019
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.

First claim

What is claimed is:

1. A circuit check method, applicable to a to-be-tested circuit, wherein the to-be-tested circuit comprises at least one first node related to a gate voltage of at least one transistor device and a plurality of second nodes, and the circuit check method comprises:
setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit;
obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device, wherein the first node voltage comprises a first maximum value and a first minimum value of the first node;
obtaining a second node voltage of each second node through analysis according to the conduction path, the endpoint voltages, and the first node voltage; and
performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage;
wherein the transistor device is one of an N-type MOS (NMOS) device or a P-type MOS (PMOS) device;
wherein when the transistor device is the N-type MOS (NMOS) device and in response to the NMOS device being turned on, a source voltage maximum value of the NMOS device is a smaller one in a gate voltage maximum value and a drain voltage maximum value of the NMOS device, and is taken as the first maximum value; and a drain voltage minimum value of the NMOS device is a source voltage minimum value, and is taken as the first minimum value; and
wherein when the transistor device is the P-type MOS (PMOS) device and in response to the PMOS device being turned on, a drain voltage maximum value of the PMOS device is a source voltage maximum value, and is taken as the first maximum value; and a source voltage minimum value of the PMOS device is a larger one in a gate voltage minimum value and a drain voltage minimum value of the PMOS device, and is taken as the first minimum value.

2. The circuit check method according to claim 1 , wherein the first node voltage considers voltage transfer of a gate and a source of the transistor device, or considers voltage transfer of the gate and a drain.

3. The circuit check method according to claim 1 , wherein the first node voltage considers voltage transfer of a gate, a source, and a threshold voltage of the transistor device, or considers voltage transfer of the gate, a drain, and the threshold voltage.

4. The circuit check method according to claim 1 , wherein the second node voltage comprises a second maximum value and a second minimum value of the second node.

5. An electronic apparatus, configured to check a to-be-tested circuit, wherein the to-be-tested circuit comprises at least one first node related to a gate voltage of at least one transistor device and a plurality of second nodes, the electronic apparatus performs a circuit check method on the to-be-tested circuit, and the circuit check method comprises:
setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit;
obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device, wherein the first node voltage comprises a first maximum value and a first minimum value of the first node;
obtaining a second node voltage of each second node through analysis according to the conduction path, the endpoint voltages, and the first node voltage; and
performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage;
wherein the transistor device is a metal oxide semiconductor (MOS) device, and the MOS device is an N-type MOS (NMOS) device, a P-type MOS (PMOS) device, or any combination of the NMOS device and the PMOS device;
wherein when the MOS device is the NMOS device and is turned on, a source voltage maximum value of the NMOS device is a smaller one in a difference between a gate voltage maximum value and a threshold voltage and a drain voltage maximum value of the NMOS device, and is taken as the first maximum value; and a drain voltage minimum value of the NMOS device is a source voltage minimum value, and is taken as the first minimum value; and
when the MOS device is the PMOS device and is turned on, a drain voltage maximum value of the PMOS device is a source voltage maximum value, and is taken as the first maximum value; and a source voltage minimum value of the PMOS device is a larger one in a difference between a gate voltage minimum value and a threshold voltage and a drain voltage minimum value of the PMOS device, and is taken as the first minimum value.

6. The electronic apparatus according to claim 5 , wherein the first node voltage considers voltage transfer of a gate and a source of the transistor device, or considers voltage transfer of the gate and a drain.

7. The electronic apparatus according to claim 5 , wherein the first node voltage considers voltage transfer of a gate, a source, and a threshold voltage of the transistor device, or considers voltage transfer of the gate, a drain, and the threshold voltage.

8. The electronic apparatus according to claim 5 , wherein the second node voltage comprises a second maximum value and a second minimum value of the second node.

Assignees

• Realtek Semiconductor Corp

Inventors

• Lin Yun-Jing
• Lee Meng-Jung
• Lo Yu-Lan
• Kao Shu-Yi

Classifications

• G01R31/002 Primary

  where the device under test is an electronic circuit · CPC title

• G01R31/2839 Primary

  using signal generators, power supplies or circuit analysers (G01R31/2879 takes precedence; multimeters G01R15/12, network analysers G01R27/28) · CPC title