Integrated transmitter slew rate calibration

Patent metadata

Field	Value
Publication number	US-11955971-B2
Application number	US-202217590668-A
Country	US
Kind code	B2
Filing date	Feb 1, 2022
Priority date	Feb 8, 2021
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

First claim

What is claimed is:

1. An integrated circuit comprising:
a signal transmitter;
a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to determine a series of output voltage levels of a selected output of the signal transmitter, wherein the output voltage levels of the selected output are captured at different respective times; and
a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the series of output voltage levels of the selected output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level of the selected output of the signal transmitter equals a first reference voltage and a second time when a second output voltage level of the selected output of the signal transmitter equals a second reference voltage, and wherein a time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

2. The integrated circuit of claim 1 , wherein the signal transmitter comprises a replica circuit element in a delay locked loop (DLL) circuit.

3. The integrated circuit of claim 1 , further comprising:
a phase interpolator circuit coupled to the sampling circuit, wherein the sampling circuit is to receive a control clock from the phase interpolator circuit to control the different respective times at which the output voltage levels of the output of the signal are sampled.

4. The integrated circuit of claim 3 , wherein to identify the first time and the second time, the measurement circuit is to compare a series of output voltage levels of the output of the signal transmitter to the corresponding reference voltages, wherein each output voltage level corresponds to a different time represented by a control code of the phase interpolator circuit.

5. The integrated circuit of claim 3 , wherein the sampling circuit comprises:
a first selection circuit to select one of two or more output signals of the signal transmitter;
a capacitor; and
a switching circuit to couple the selected one of the two or more output signals of the signal transmitter received from the first selection circuit to the capacitor, wherein the switching circuit is controlled by a pulse generator based on the control clock from the phase interpolator circuit.

6. The integrated circuit of claim 3 , wherein the signal transmitter, the phase interpolator circuit, the sampling circuit, and the measurement circuit are coupled to control logic to receive respective control signals, wherein the signal transmitter to receive a slew rate adjustment control signal from the control logic.

7. The integrated circuit of claim 1 , wherein the measurement circuit comprises:
a second selection circuit to select an output of the sampling circuit, wherein the output of the sampling circuit comprises at least one of the first output voltage level or the second output voltage level; and
a comparator circuit to compare the selected output of the sampling circuit to at least one of the first reference voltage or the second reference voltage.

8. The integrated circuit of claim 1 , wherein the first reference voltage comprises a low reference voltage associated with a transition of the output of the signal transmitter from a first voltage state to a second voltage state, and wherein the second reference voltage comprises a high reference voltage associated with the transition of the output of the signal transmitter from the first voltage state to the second voltage state.

9. A method of operation of a slew rate calibration circuit, the method comprising:
determining a series of output voltage levels of a selected output of a signal transmitter, wherein the output voltage levels of the selected output are captured at different respective times;
comparing the series of output voltage levels of the selected output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level of the selected output of the signal transmitter equals a first reference voltage and a second time when a second output voltage level of the selected output of the signal transmitter equals a second reference voltage;
determining a time difference between the first time and the second time; and
configuring a slew rate adjustment control of the signal transmitter based on the time difference between the first time and the second time.

10. The method of claim 9 , wherein the signal transmitter comprises a replica circuit element in a delay locked loop (DLL) circuit.

11. The method of claim 9 , further comprising:
receiving a control clock from a phase interpolator circuit to control the different respective times at which the output voltage levels of the output of the signal are sampled.

12. The method of claim 11 , wherein identifying the first time and the second time comprises comparing a series of output voltage levels of the output of the signal transmitter to the corresponding reference voltages, wherein each output voltage level corresponds to a different time represented by a control code of the phase interpolator circuit.

13. The method of claim 11 , further comprising:
selecting one of two or more output signals of the signal transmitter; and
coupling the selected one of the two or more output signals of the signal transmitter received from the first selection circuit to a capacitor based on the control clock from the phase interpolator circuit.

14. The method of claim 9 , wherein the first reference voltage comprises a low reference voltage associated with a transition of the output of the signal transmitter from a first voltage state to a second voltage state, and wherein the second reference voltage comprises a high reference voltage associated with the transition of the output of the signal transmitter from the first voltage state to the second voltage state.

15. A memory module comprising:
one or more memory devices; and
a data buffer coupled to the one or more memory devices, the data buffer comprising:
a replica signal transmitter;
a sampling circuit coupled to the replica signal transmitter, wherein the sampling circuit is to determine a series of output voltage levels of a selected output of the replica signal transmitter, wherein the output voltage levels of the selected output are captured at different respective times; and
a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the series of output voltage levels of the selected output of the replica signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level of the selected output of the signal transmitter equals a first reference voltage and a second time when a second output voltage level of the selected output of the signal transmitter equals a second reference voltage, and wherein a time difference between the first time and the second time is used to configure a slew rate adjustment control of the replica signal transmitter.

16. The memory module of claim 15 , further comprising:
a phase interpolator circuit coupled to the sampling circuit, wherein the sampling circuit is to receive a control clock from the phase interpolator circuit to control the different respective times at which the output voltage levels of the output of the signal are sampled.

17. The memory module of claim 16 , wherein the sampling circuit comprises:
a first selection circuit to select one of two or more output signals of the replica signal tr

Assignees

• Rambus Inc

Inventors

• Palmer Robert E
• Fuller Andrew
• Su Hsuan-Jung

Classifications

• H03K19/09429 Primary

  one of the states being the high impedance or floating state · CPC title

• G01R31/31937

  Timing aspects, e.g. measuring propagation delay (G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24) · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title