Power semiconductor device with an auxiliary gate structure

Patent metadata

Field	Value
Publication number	US-11955478-B2
Application number	US-202117350490-A
Country	US
Kind code	B2
Filing date	Jun 17, 2021
Priority date	May 7, 2019
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. A pull-down network for the switching-off of the high threshold voltage GaN transistor may be formed by additional auxiliary low-voltage GaN transistors and resistive elements connected with the low-voltage auxiliary GaN transistor.

First claim

What is claimed is:

1. A III-nitride power semiconductor based heterojunction device, comprising:
an active heterojunction transistor formed on a substrate, the active heterojunction transistor comprising:
a first III-nitride semiconductor region comprising a first heterojunction comprising an active two dimensional carrier gas of second conductivity type;
a first terminal operatively connected to the III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal and operatively connected to the III-nitride semiconductor region;
an active gate region formed over the III-nitride semiconductor region, the active gate region being formed between the first terminal and the second terminal;

an auxiliary heterojunction transistor formed on the said substrate or a further substrate, the auxiliary heterojunction transistor comprising:
a second III-nitride semiconductor region comprising a second heterojunction comprising an auxiliary two dimensional carrier gas of second conductivity type;
a first additional terminal operatively connected to the second III-nitride semiconductor region;
a second additional terminal laterally spaced from the first additional terminal and operatively connected to the second III-nitride semiconductor region;
an auxiliary gate region formed over the second III-nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;

wherein the first additional terminal is operatively connected with the auxiliary gate region, and wherein the second additional terminal is operatively connected with the active gate region; and
wherein the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and wherein the heterojunction power device further comprises a second auxiliary heterojunction transistor which is operatively connected in parallel with the first auxiliary transistor, and wherein the first additional terminal of the first auxiliary heterojunction transistor is operatively connected to a source terminal of the second auxiliary heterojunction transistor, and the second additional terminal of the first auxiliary heterojunction transistor is operatively connected to a drain terminal of the second auxiliary heterojunction transistor; and
wherein the heterojunction device comprises a shielding and/or decoupling structure disposed between the active heterojunction transistor and the auxiliary heterojunction transistor.

2. The heterojunction power device according to claim 1 , further comprising an active Miller clamp which comprises a logic inverter and an actively switched transistor which acts as a pull down network, and wherein the logic inverter comprises a resistor or resistive element and an enhancement mode transistor.

3. The heterojunction power device according to claim 1 , wherein the shielding and/or decoupling structure comprises any of: one or more layers of two-dimensional carrier gas of the first and/or second conductivity type; one or more metal layers; and/or one or more conductive layers; and
wherein the shielding and/or decoupling structure is operatively connected to one of: the first terminal; a potential; or ground.

4. A depletion mode III-nitride semiconductor based heterojunction device, comprising:
a substrate;
a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type;
a first terminal operatively connected to the III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region;
at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and
an active gate region formed over the at least two highly doped semiconductor regions;
wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension and wherein the second dimension is perpendicular to the first dimension; and
at least two rows of active gate regions each formed over the at least two highly doped semiconductor regions;
wherein the depletion mode III-nitride semiconductor based heterojunction device has two threshold levels, and wherein the depletion mode III-nitride semiconductor based heterojunction device is configurable to actively switch between:
(i) an off-state, wherein the gate voltage with respect to the source voltage is lower than the first threshold;
(ii) a high resistance mode, wherein the gate voltage with respect to the source voltage is between the first and second threshold levels; and
(iii) a low resistance mode, wherein the when the gate voltage with respect to the source voltage is higher than the second threshold.

5. A heterojunction chip having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal, wherein the heterojunction chip further comprises;
at least one main power heterojunction transistor, wherein the at least one main power heterojunction transistor comprises an internal gate terminal, a source terminal and a drain terminal, wherein the source terminal of the at least one main power heterojunction transistor is operatively connected to the low voltage terminal and the drain terminal of the at least one main power heterojunction transistor is operatively connected to the high voltage terminal;
an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, wherein the auxiliary gate circuit is operatively connected to the internal gate terminal of the at least one main power heterojunction transistor and to the control terminal;
a pull-down circuit comprising at least one non-linear element and at least one second low-voltage heterojunction transistor, the non-linear element comprising a potential divider for driving the gate terminal of the at least one second low-voltage heterojunction transistor, wherein the pull-down circuit is operatively connected to an internal gate terminal of the at least one first low-voltage heterojunction transistor and to the source terminal of the at least one main power heterojunction transistor;
a current control circuit comprising at least one resistor, wherein the current control circuit is operatively connected to the control terminal and to the pull-down circuit; and
wherein the auxiliary gate and current control circuits at least partially control a voltage and a current into the internal gate of the at least one main power heterojunction transistor; and
wherein the current control circuit at least partially controls a current into the pull down circuit and at least partially determines a control terminal voltage level at which the pull-down circuit actively pulls down a gate voltage of the at least one first low-voltage heterojunction transistor to clamp a voltage of the internal gate of the at least one main power heterojunction transistor.

6. The heterojunction chip of claim 5 , wherein the potential divider comprises at least one of a resistive, capacitive, diode or transistor elements; and
the potential divider has at least one connection to an internal gate of the at least one second low-voltage heterojunction transistor.

7. The heterojunction chip of claim 5 , wherein the potential divider is operatively connected to at least one of the current control circuit, the internal gate of the at least one main power heterojunction transistor, and

Assignees

• Cambridge Entpr Ltd
• Cambridge Gan Devices Ltd

Inventors

• Arnold Martin
• Efthymiou Loizos
• Udrea Florin
• Longobardi Giorgia
• Findlay John William

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10D64/411

  for FETs · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title