Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays

Patent metadata

Field	Value
Publication number	US-11955156-B2
Application number	US-202217589603-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Apr 20, 2016
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

First claim

We claim:

1. A method of reading memory cells of a memory array, comprising:
providing the memory array to have metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors as the memory cells, with a first data state of the memory cells corresponding to a first polarization mode of ferroelectric material within the MFMIS transistors and a second data state of the memory cells corresponding to a second polarization mode of the ferroelectric material within the MFMIS transistors;
the individual MFMIS transistors comprising a gate and a pair of source/drain regions;
the memory array comprising rows and columns of the MFMIS transistors, each of the rows comprising a first transistor and a second transistor that share a common source/drain region and common contact extending upward from the common source/drain regions and between gates of the first and second transistors, a line of symmetry passing through the common source/drain region and common contact with the first transistor being a mirror image of the second transistor across the line of symmetry;
MFMIS transistors in a common row as one another having all of their gates electrically coupled to one another through a wordline;
MFMIS transistors in a common column as one another sharing a pair of digit lines; a first of the digit lines being connected to one source/drain region of each of the MFMIS transistors in said common column, and a second of the digit lines being connected to the other source/drain region of each of the MFMIS transistors in said common column;
identifying an active row comprising memory cells which are to be read; and
providing a voltage difference between the first and second digit lines for all of the memory cells within the active row while simultaneously providing a bias voltage along the wordline of the active row.

2. The method of claim 1 wherein the all of the source/drain regions of MFMIS transistors within a common column are shared between two adjacent MFMIS transistors.

3. The method of claim 1 wherein each of the MFMIS transistors comprises:
ferroelectric material wrapping partially around the gate;
metal-containing material outward of the ferroelectric material and extending along the ferroelectric material to wrap partially around the gate; and
gate dielectric outward of the metal-containing material and extending along the metal-containing material to wrap partially around the gate.

4. The method of claim 3 wherein the ferroelectric material, metal-containing material and gate dielectric are each configured as a separate elbow-shaped container, with said elbow-shaped containers nesting within one another.

5. The method of claim 4 wherein the elbow-shaped containers have corners with angles of about 90°.

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak Nirmal
• Kinney Wayne

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• G11C11/2275 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title