Framework for obfuscation based watermarking

Patent metadata

Field	Value
Publication number	US-11954201-B2
Application number	US-202117224559-A
Country	US
Kind code	B2
Filing date	Apr 7, 2021
Priority date	Apr 9, 2020
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

The present disclosure describes systems, apparatuses, and methods for obfuscation-based intellectual property (IP) watermark labeling. One such method comprises identifying, by one or more computing processors, a specific net within an integrated circuit design that is likely to be used in a malicious attack; and adding additional nets to the integrated circuit design that add additional logic states to a finite state machine present in the integrated circuit design. The additional logic states comprise watermarking states for performing authentication of the integrated circuit design, in which a watermark digest can be captured upon application of secret key inputs to the additional nets. Other methods, systems, and apparatuses are also presented.

First claim

The invention claimed is:

1. A method comprising:
identifying, by one or more computing processors, a specific net within an integrated circuit design that is likely to be used in a malicious attack;
adding, by the one or more computing processors, additional nets to the integrated circuit design that add additional logic states to a finite state machine present in the integrated circuit design, wherein the additional logic states comprise watermarking states for performing authentication of the integrated circuit design, wherein a state transition to the watermarking states is dependent upon on an output of the specific net, wherein an output of the additional nets is governed by one or more secret key inputs applied to the additional nets, wherein the additional nets comprise a multiple shift input register (MISR) followed by an XOR network;
applying, by the one or more computing processors, the secret key inputs to the additional nets;
capturing, by the one or more computing processors at an output of a leakage enabling circuit, a side channel signature upon application of the secret key inputs to the additional nets; and
deciphering, by the one or more computing processors, a watermark digest from the side channel signature based on a switching activity of the output of the leakage enabling circuit, wherein the MISR applies values of individual nets over multiple timesteps to create an n-bit digest and the XOR network compresses the n-bit digest to a final k-bit watermark digest, where k<n,
wherein when the integrated circuit design is being authenticated, a manufactured integrated circuit design is traversed to the watermarking states with an application of specific key inputs, wherein the additional nets becomes functional in generating a correct watermark digest response only at the watermarking states, wherein if responses match golden references stored during an enrollment process of the integrated circuit design, the manufactured integrated circuit design is recognized as an authentic device, wherein the responses correspond to the watermark digest and the specific key inputs correspond to the secret key inputs.

2. The method of claim 1 , wherein the watermark digest is a fixed length pattern that is representative of the integrated circuit design.

3. The method of claim 1 , wherein challenge-response pairs for the manufactured integrated circuit design are stored in a database prior to deployment of the integrated circuit design, wherein the watermark digest for the secret keys input is compared with a challenge-response pair from the database.

4. The method of claim 1 , wherein the specific key inputs are applied in a sequential order.

5. The method of claim 1 , further comprising coupling a physical unclonable function (PUF) circuit to the output of the additional nets, wherein traversal of the logic states of the additional nets is required to access an input logic state of the PUF circuit, wherein a unique authentication signature for an individual integrated circuit is captured via an output of the PUF circuit.

6. The method of claim 1 , wherein the leakage enabling circuit comprises a capacitor, wherein an output of the XOR network is coupled to the capacitor, wherein the side channel signature of the capacitor is captured to form the watermark digest.

7. The method of claim 1 , wherein the secret key inputs comprise a series of test vectors, the method further comprising generating the test vectors using reinforcement learning.

8. The method of claim 5 , wherein the PUF circuit is enabled to output the unique authentication signature upon application of a correct input key sequence for the PUF circuit.

9. The method of claim 6 , wherein the MISR is a linear-feedback shift register and the XOR network is an XOR gate.

10. A system comprising:
a processor and memory, wherein the memory stores instructions that, in response to execution by the processor, cause the processor to perform operations comprising:
identifying a specific net within an integrated circuit design that is likely to be used in a malicious attack;
adding additional nets to the integrated circuit design that add additional logic states to a finite state machine present in the integrated circuit design, wherein the additional logic states comprise watermarking states for performing authentication of the integrated circuit design, wherein a state transition to the watermarking states is dependent upon on an output of the specific net, wherein an output of the additional nets is governed by one or more secret key inputs applied to the additional nets, wherein the additional nets comprise a multiple shift input register (MISR) followed by an XOR network;
applying the secret key inputs to the additional nets;
capturing, at an output of a leakage enabling circuit, a side channel signature upon application of the secret key inputs to the additional nets; and
deciphering a watermark digest from the side channel signature based on a switching activity of the output of the leakage enabling circuit, wherein the MISR applies values of individual nets over multiple timesteps to create an n-bit digest and the XOR network compresses the n-bit digest to a final k-bit watermark digest, where k<n,

wherein when the integrated circuit design is being authenticated, a manufactured integrated circuit design is traversed to the watermarking states with an application of specific key inputs, wherein the additional nets becomes functional in generating a correct watermark digest response only at the watermarking states, wherein if responses match golden references stored during an enrollment process of the integrated circuit design, the manufactured integrated circuit design is recognized as an authentic device, wherein the responses correspond to the watermark digest and the specific key inputs correspond to the secret key inputs.

11. The system of claim 10 , wherein the watermark digest is a fixed length pattern that is representative of the integrated circuit design.

12. The system of claim 10 , wherein the secret key inputs are applied in a sequential order.

13. The system of claim 10 , further comprising a physical unclonable function (PUF) circuit coupled to the output of the additional nets, wherein traversal of the logic states of the additional nets is required to access an input logic state of the PUF circuit, wherein an output of the PUF circuit is configured to signal a unique authentication signature for an individual integrated circuit.

14. The system of claim 10 , wherein the leakage enabling circuit is characterized by specific switching activity based on a specific input sequence, wherein the leakage enabling circuit comprises a capacitor, wherein an output of the XOR network is coupled to the capacitor, wherein the side channel signature of the capacitor is captured to form the watermark digest.

15. The system of claim 10 , wherein the secret key inputs comprise a series of test vectors.

16. The system of claim 13 , wherein the PUF circuit is enabled to output the unique authentication signature upon application of a correct input key sequence for the PUF circuit.

17. The system of claim 14 , wherein the MISR is a linear-feedback shift register and the XOR network is an XOR gate.

Assignees

• Univ Florida

Inventors

• Bhunia Swarup
• Hoque Tamzidul
• Nair Abhishek Anil
• Sristi Lakshmiprasanna Sriramakumara Patanjali

Classifications

• G06F21/56 Primary

  Computer malware detection or handling, e.g. anti-virus arrangements · CPC title

• G06F2221/034

  Test or assess a computer or a system · CPC title

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/16

  Program or content traceability, e.g. by watermarking · CPC title