Accessing encoded blocks of data

Patent metadata

Field	Value
Publication number	US-11954028-B2
Application number	US-202217657498-A
Country	US
Kind code	B2
Filing date	Mar 31, 2022
Priority date	Mar 31, 2021
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

There is disclosed a method of storing an encoded block of data in memory comprising encoding a block of data elements and determining a memory location (26) at which the encoded block of data is to be stored. The memory location (26) at which the encoded block of data is stored is then indicated in a header (406) for the encoded block of data by including in the header a memory address value (407) together with a modifier value (500) representing a modifier that is to be applied to the memory address value (407) when determining the memory location (26). When the encoded block of data is to be retrieved, the header (406) is read and processed to determine the memory location (26).

First claim

What is claimed is:

1. A method of storing an encoded block of data in memory, the method comprising:
encoding a block of data elements of an array of data elements to generate an encoded block of data that represents the block of data elements;
determining a memory location at which the encoded block of data is to be stored;
generating a header for the encoded block of data that indicates the memory location at which the encoded block of data is stored, wherein the memory location is indicated by including in the header a memory address value together with a modifier value representing a modifier that is to be applied to the memory address value when determining the memory location; and
writing out the header and the encoded block of data to memory, wherein the encoded block of data is stored in memory at the location indicated in the header for the encoded block of data;
the method further comprising, when generating the header:
determining, from a plurality of available modifiers, which of the plurality of available modifiers should be used together with the memory address value for indicating the memory location at which the encoded block of data is to be stored, and
including a respective modifier value representing the determined modifier in the header together with the memory address value, wherein
one of the available modifiers comprises a zero modifier that does not modify the memory address value, and wherein
the respective modifier value is stored using bits in the memory address field that would otherwise be usable for storing the memory address value.

2. The method of claim 1 , wherein the respective modifier value represents a scale factor that is to be applied to the memory address value when determining the memory location.

3. The method of claim 1 , wherein the memory address value represents an offset and wherein the respective modifier can be applied to the offset to generate a modified offset that can be used to determine the memory location.

4. The method of claim 1 , comprising storing, in sequence, a plurality of encoded blocks of data in respective memory locations, wherein the encoded blocks of data are stored at progressively increasing memory locations, and wherein the method comprises initially setting the respective modifier value to a zero modifier and increasing the respective modifier value when a memory location for an encoded block of data exceeds a memory address range that can be accessed using the zero modifier.

5. The method of claim 1 , wherein the encoded blocks of data are each allocated a fixed amount of space in the memory and are stored in the memory at pre-defined positions that are aligned with the respective boundaries for the allocated amounts of space.

6. The method of claim 1 , further comprising when determining, from a plurality of available modifiers, which of the plurality of available modifiers should be used together with the memory address value for indicating the memory location at which the encoded block of data is to be stored:
determining whether a memory location at which the encoded block of data is to be stored would exceed a memory address range that could otherwise be accessed based on a current modifier value;
and when it is determined that the memory location at which the encoded block of data is to be stored would exceed the memory address range that could otherwise be accessed based on the current modifier value, selecting a different modifier from the plurality of modifiers such that the memory location at which the encoded block of data is to be stored can be accessed.

7. The method of claim 6 , further comprising progressively increasing the modifier as the required memory address range increases.

8. The method of claim 1 , wherein the modifier value is stored using bits in the memory address field that would otherwise be usable for storing the memory address value by:
truncating the memory address by removing a number of bits from the memory address, and storing the modifier in the position of the removed bits.

9. The method of claim 8 , wherein a number of the least significant bits in the memory address value are truncated and the modifier is stored using these least significant bits.

10. The method of claim 1 , further comprising retrieving the encoded block of data from memory, the retrieving comprising steps of:
reading from the header for the encoded block of data that represents the block of data elements of the array of data elements from memory;
determining the memory location for the encoded block of data by applying the modifier to the memory address value;
reading in data for the encoded block of data from memory from the determined memory location; and
decoding the encoded block of data to derive at least one data value for a data element of the encoded block of data.

11. An apparatus for storing encoded blocks of data in memory, the apparatus comprising:
an encoding circuit configured to: encode a block of data elements of an array of data elements to generate an encoded block of data that represents the block of data elements;
a header generating circuit configured to:
determine a memory location at which the encoded block of data is to be stored; and
generate a header for the encoded block of data, wherein the header indicates the memory location at which the encoded block of data is stored, wherein the memory location is indicated by the header generating circuit including in the header a memory address value together with a modifier value representing a modifier that is to be applied to the memory address value when determining the memory location; and
a write out control circuit configured to write out the header and the encoded block of data to memory, wherein the encoded block of data is stored in memory at the location indicated in the header for the encoded block of data;
wherein the modifier value is stored using a number of bits in the memory address field that would otherwise be usable for storing the memory address value.

12. The apparatus of claim 11 , wherein the header generating circuit is configured to determine, from a plurality of available modifiers, which of the plurality of available modifiers should be used together with the memory address value for indicating the memory location at which the encoded block of data is to be stored, and including the modifier value representing the determined modifier in the header together with the memory address value.

13. The apparatus of claim 12 , wherein one of the available modifiers comprises a zero modifier that does not modifier the memory address value.

14. The apparatus of claim 13 , wherein when storing, in sequence, a plurality of encoded blocks of data in respective memory locations, wherein the encoded blocks of data are stored at progressively increasing memory locations, the header-generating apparatus is configured to initially set the modifier value to a zero modifier and increase the modifier value when a memory location for an encoded block of data exceeds a memory address range that can be accessed using the zero modifier.

15. The apparatus of claim 11 , wherein the encoded blocks of data are each allocated a fixed amount of space in the memory and are stored in the memory at pre-defined positions that are aligned with the respective boundaries for the allocated amounts of space.

16. The apparatus of claim 11 , wherein the array of data elements corresponds to a frame generated by a graphics processing system, and wherein the memory corresponds to a frame buffer for the graphics processing system and/or for a displ

Assignees

• Advanced Risc Mach Ltd

Inventors

• Fielding Edvard
• Wang Jian
• Fries Jakob Axel
• Giliberto Carmelo

Classifications

• G06F12/0646 Primary

  Configuration or reconfiguration · CPC title

• G06F2212/40

  Specific encoding of data in memory or cache · CPC title

• G06F12/06 Primary

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• H04N19/46 Primary

  Embedding additional information in the video signal during the compression process (H04N19/517, H04N19/68, H04N19/70 take precedence) · CPC title