Parasitic commands for equalizing logical unit capacity in asymmetric multiple actuator hard disk drive

Patent metadata

Field	Value
Publication number	US-11954027-B2
Application number	US-202217678765-A
Country	US
Kind code	B2
Filing date	Feb 23, 2022
Priority date	Feb 23, 2022
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A multiple-actuator hard disk drive includes a first actuator associated with a first logical unit and configured to operate on a first set of disk surfaces, a second actuator associated with a second logical unit and configured to operate on a second set of disk surfaces greater than the first set, and a controller accessing a mapping of logical memory addresses to physical memory locations. The mapping maps the first logical unit to the physical memory locations of the first set of surfaces and a parasitic portion of the second set of surfaces, and maps the second logical unit to the physical memory locations of the second set of surfaces exclusive of the parasitic portion of the second set of surfaces. Thus, data transfer commands performed on the parasitic portion are executed by one actuator while credit is given to the logical unit associated with the other actuator.

First claim

What is claimed is:

1. A data storage device comprising:
a first actuator assembly associated with a host-addressable first logical unit and configured to operate on a corresponding first set of disk media surfaces;
a second actuator assembly associated with a host-addressable second logical unit and configured to operate on a corresponding second set of disk media surfaces greater than the first set; and
an electronic controller communicatively coupled with the first actuator assembly and the second actuator assembly, the controller configured to access:
a mapping of logical memory addresses to physical memory locations, the mapping comprising:
a first portion corresponding to the first logical unit associated with the first actuator assembly, wherein the first portion maps the first logical unit to the physical memory locations of the first set of disk media surfaces and a parasitic portion of the second set of disk media surfaces, such that operations by the second actuator assembly on the parasitic portion of the second set of disk media surfaces are attributed to the first logical unit associated with the first actuator assembly, and
a second portion corresponding to the second logical unit, wherein the second portion maps the second logical unit to the physical memory locations of the second set of disk media surfaces exclusive of the parasitic portion of the second set of disk media surfaces, such that operations by the second actuator assembly on the parasitic portion of the second set of disk media surfaces are attributed to the first logical unit associated with the first actuator assembly.

2. The data storage device of claim 1 , wherein the parasitic portion of physical memory locations of the second set of disk media surfaces corresponds to an entire surface available for host data storage of at least one disk medium of the second set of disk media.

3. The data storage device of claim 1 , wherein the parasitic portion of physical memory locations of the second set of disk media surfaces corresponds to a respective band of host-addressable memory addresses on one or more of the second set of disk media surfaces.

4. The data storage device of claim 3 , wherein the parasitic portion of physical memory locations of the second set of disk media surfaces corresponds to a respective inner-diameter band of host-addressable memory addresses on one or more of the second set of disk media surfaces.

5. The data storage device of claim 3 , wherein the parasitic portion of physical memory locations of the second set of disk media surfaces corresponds to a respective inner-diameter band of host-addressable memory addresses on each of the second set of disk media surfaces.

6. The data storage device of claim 1 , wherein the parasitic portion of physical memory locations of the second set of disk media surfaces corresponds to a respective band of host-addressable memory addresses on each of the second set of disk media surfaces.

7. The data storage device of claim 1 , the controller further configured to:
receive from a host an input/output (TO) operation request addressed to the first logical unit;
based on the mapping, send a command to the second actuator assembly to execute at least a portion of the IO operation involving the parasitic portion of the second set of disk media surfaces; and
return to the host a response identified as from the first logical unit.

8. The data storage device of claim 7 , wherein the controller is further configured to:
reduce power to the first actuator assembly to reduce input/output operations per second (IOPS) of the first actuator assembly.

9. A method of controlling a hard disk drive asymmetric multi-actuator system, wherein a first actuator assembly is configured to operate on a corresponding first number of first disk media surfaces and a second actuator assembly is configured to operate on a corresponding higher second number of second disk media surfaces, the method comprising:
receiving from a host an input/output (TO) operation request addressed to a host-addressable first logical unit of memory assigned to the first actuator assembly;
based on a pre-configured fixed data structure mapping logical memory addresses to physical memory locations of the first and second disk media surfaces, wherein the data structure comprises a first portion corresponding to the first logical unit and maps the first logical unit to physical memory locations of the first disk media surfaces and a portion of physical memory locations of the second disk media surfaces, sending a command to the second actuator assembly to execute at least a portion of the TO operation involving the portion of physical memory locations of the second disk media surfaces mapped to the first logical unit of memory assigned to the first actuator assembly;
the second actuator assembly executing the portion of the TO operation involving the portion of physical memory locations of the second disk media surfaces mapped to the first logical unit of memory assigned to the first actuator assembly; and
returning to the host a response identified as from the first logical unit.

10. The method of claim 9 , further comprising:
reducing power to the first actuator assembly to reduce input/output operations per second (IOPS) of the first actuator assembly.

11. The method of claim 9 , wherein the portion of physical memory locations of the second disk media surfaces corresponds to an entire host-addressable surface of one of the second disk media.

12. The method of claim 9 , wherein the portion of physical memory locations of the second disk media surfaces corresponds to a respective band of host-addressable memory addresses on one or more of the second disk media surfaces.

13. The method of claim 9 , wherein the portion of physical memory locations of the second disk media surfaces corresponds to a respective inner-diameter band of host-addressable memory addresses on each of the second disk media surfaces.

14. The method of claim 13 , further comprising:
in response to a configuration request for a limited partition of memory for host workload, based on the fixed data structure:
allocating a respective outer diameter band of host-addressable memory addresses on the first disk media surfaces to the physical memory locations of the first disk media surfaces of the first logical unit; and
allocating a respective outer diameter band of host-addressable memory addresses on the second disk media surfaces to the physical memory locations of the second disk media surfaces of the second logical unit.

15. A controller circuitry for an asymmetric multi-actuator hard disk drive, wherein a first actuator assembly is configured to operate on a corresponding first number of first disk media surfaces and a second actuator assembly is configured to operate on a corresponding higher second number of second disk media surfaces, the controller circuitry storing or accessing one or more sequences of instructions which, when executed by one or more processors, cause performance of:
receiving from a host an input/output (TO) operation request addressed to a host-addressable first logical unit of memory assigned to the first actuator assembly;
based on a fixed data structure mapping logical memory addresses to physical memory locations of the first and second disk media surfaces, wherein the data structure comprises a first portion corresponding to the first logical unit and maps the first logical unit to physical memory locations of the first disk media surfaces and a portion of physical memory locations of the second disk media surfaces, sen

Assignees

• Western Digital Tech Inc

Inventors

• Hall David
• Khalili Ali

Classifications

• G11B5/4813

  Mounting or aligning of arm assemblies, e.g. actuator arm supported by bearings, multiple arm assemblies, arm stacks or multiple heads on single arm (G11B5/484 takes precedence) · CPC title

• G06F12/063 Primary

  for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42) · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0635

  by changing the path, e.g. traffic rerouting, path reconfiguration · CPC title

• G06F3/0676 Primary

  Magnetic disk device · CPC title