Memory cell, capacitive memory structure, and methods thereof

Patent metadata

Field	Value
Publication number	US-11950430-B2
Application number	US-202017085141-A
Country	US
Kind code	B2
Filing date	Oct 30, 2020
Priority date	Oct 30, 2020
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

First claim

What is claimed is:

1. A memory cell comprising:
a first electrode;
a second electrode; and
a memory structure disposed between the first electrode and the second electrode,
the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode comprises a plurality of layers comprising:
a first electrode layer in direct contact with the memory structure, wherein the first electrode layer comprises a first material having a first microstructure comprising a first average grain size;
a functional layer in direct contact with the first electrode layer; and
a second electrode layer in direct contact with the functional layer, the second electrode layer contacting, from among the plurality of layers, only the functional layer, wherein the second electrode layer comprises a second material having a second microstructure different from the first microstructure for reducing a leakage current of the memory capacitor, wherein the second microstructure comprises a second average grainsize that differs from the first average grain size, a second crystallographic texture that differs from the second crystallographic texture, and a second grain size distribution that differs from the second grain size distribution, wherein the first electrode layer, the functional layer, and the second electrode layer form a planar electrode layer stack of the memory capacitor, wherein the functional layer is disposed between the first layer and the second layer in the planar electrode layer stack.

2. The memory cell according to claim 1 ,
wherein the first microstructure further differs from the second microstructure in at least one of: granularity, grain size distribution, number of grain boundaries, spatial density of grain boundaries, shape of grain boundaries, chemical composition of grain boundaries, regions between two adjacent grains, content of defects, type of defects, crystallographic texture, and/or chemical composition of defects.

3. The memory cell according to claim 1 ,
wherein the first material of the first electrode layer has a first weight percentage of oxygen, and a second material of the second electrode layer has a second weight percentage of oxygen different from the first weight percentage of oxygen.

4. The memory cell according to claim 1 ,
wherein the first material of the first electrode layer has a first crystal structure and the second material of the second electrode layer has a second crystal structure different from the first crystal structure.

5. The memory cell according to claim 1 ,
wherein the first material of the first electrode layer comprises at least one of: Platinum, Tantalum, Indium, Iridium, Rhenium, Rhodium, Ruthenium, Titanium, Osmium, Molybdenum, Chromium, Tungsten, Aluminum, Cobalt.

6. The memory cell according to claim 1 ,
wherein the first electrode layer has a first thickness and the second electrode layer has a second thickness different from the first thickness.

7. The memory cell according to claim 1 ,
wherein the first electrode layer has a first electrical conductivity, the second electrode layer has a second electrical conductivity different from the first electrical conductivity.

8. The memory cell according to claim 1 ,
wherein the functional layer is an oxygen absorbing layer or an oxygen diffusion barrier layer.

9. The memory cell according to claim 1 ,
wherein the first electrode layer comprises a first rate of diffusion of oxygen and the second electrode layer comprises a second rate of diffusion of oxygen different from the first rate of diffusion of oxygen.

10. The memory cell according to claim 1 ,
wherein the at least one of the first electrode and the second electrode further comprises a second functional layer in direct contact with the second electrode layer; and a third electrode layer in direct contact with the second functional layer, the third electrode layer having a third microstructure different from the second microstructure and from the first microstructure.

11. The memory cell according to claim 1 ,
wherein the memory structure comprises one or more remanent polarizable layers.

12. A memory cell comprising:
a first electrode;
a second electrode; and
a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode comprises:
a first electrode layer in direct contact with the memory structure, wherein the first electrode layer comprises a first electrical conductivity;
a functional layer in direct contact with the first electrode layer; and
a second electrode layer in direct contact with the functional layer, wherein the functional layer comprises a monolayer of an electrically insulating material interposed between the first electrode layer and the second electrode layer, wherein the second electrode layer has a second electrical conductivity less than the first electrical conductivity for reducing a leakage current of the memory capacitor, wherein the functional layer is disposed between the first electrode layer and the second electrode layer, and wherein the first electrode layer is not in direct contact with the second electrode layer.

13. The memory cell according to claim 12 ,
wherein the first electrical conductivity is at least two times greater than the second electrical conductivity.

14. The memory cell according to claim 12 ,
wherein the functional layer has the same lateral dimension as the first electrode layer and as the second electrode layer.

15. The memory cell according to claim 1 , the memory cell further comprising:
a field-effect transistor structure comprising a gate electrode, wherein the gate electrode is electrically conductively connected to either the first electrode or the second electrode of the memory capacitor.

16. The memory cell according to claim 15 , wherein the gate electrode comprises a conductive layer at a floating gate node of the field-effect transistor structure, wherein the gate electrode is electrically conductively connected to the second electrode layer of the memory capacitor at the floating gate node.

17. The memory cell according to claim 16 , the memory cell further comprising:
an intermediate conductive structure that electrically conductively connects the conductive layer of the floating gate node to the second electrode layer of the memory capacitor.

18. The memory cell according to claim 1 , wherein the functional layer comprises a monolayer of an electrically insulating material interposed between the first electrode layer and the second electrode layer.

Assignees

• Ferroelectric Memory Gmbh

Inventors

• Müller Stefan Ferdinand
• Polakowski Patrick

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10D1/712

  being rough surfaces, e.g. using hemispherical grains · CPC title

• H10D1/694 Primary

  comprising noble metals or noble metal oxides · CPC title

• H10D1/688

  comprising barrier layers to prevent diffusion of hydrogen or oxygen · CPC title

• H10D1/684

  the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers · CPC title