Memory architecture with shared bitline at back-end-of-line

Patent metadata

Field	Value
Publication number	US-11950407-B2
Application number	US-202016828507-A
Country	US
Kind code	B2
Filing date	Mar 24, 2020
Priority date	Mar 24, 2020
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A memory device, comprising:
a first memory cell including a first storage cell and a first transistor to control access to the first storage cell;
a second memory cell including a second storage cell and a second transistor to control access to the second storage cell; and
a shared contact electrode that is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, and coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device, wherein the shared contact is on a side of a first channel area and a second channel area opposite a first gate electrode and a second gate electrode of the first and second transistors, respectively, and wherein the first transistor further includes the first gate electrode coupled to a first word line, and the second transistor further includes the second gate electrode coupled to a second word line.

2. The memory device of claim 1 , wherein the first word line and the second word line are located in a same metal layer at back end of the line.

3. The memory device of claim 1 , wherein the first gate electrode is coupled to the first word line by a first short via, and the second gate electrode is coupled to the second word line by a second short via.

4. The memory device of claim 1 , wherein the shared contact electrode is located in a first metal layer, and the first gate electrode or the second gate electrode is located in a second metal layer, and the second metal layer is separated from the first metal layer by an ILD layer.

5. The memory device of claim 4 , wherein the ILD layer includes a material selected from the group consisting of silicon dioxide (SiO 2 ), carbon doped oxide (CDO), silicon nitride, perfluorocyclobutane, polytetrafluoroethylene, fluorosilicate glass (FSG), organic polymer, silsesquioxane, siloxane, and organosilicate glass.

6. The memory device of claim 1 , wherein the first transistor further includes the first channel area separating the shared contact electrode and the first gate electrode, the second transistor further includes the second channel area separating the shared contact electrode and the second gate electrode, and wherein the first channel area and the second channel area form a continuous channel area.

7. The memory device of claim 6 , wherein the continuous channel area includes a material selected from the group consisting of CuS 2 , CuSe 2 , WSe 2 , indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, Si 2 BN, stanene, phosphorene, molybdenite, poly-III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC), molybdenum and sulfur, and a group-VI transition metal dichalcogenide.

8. The memory device of claim 1 , wherein the first transistor further includes a first contact electrode coupled to the source area or the drain area of the first transistor, the first memory cell includes a first capacitor, and the first contact electrode is coupled to a first plate within the first capacitor; and the second transistor further includes a second contact electrode coupled to the source area or the drain area of the second transistor, the second memory cell includes a second capacitor, and the second contact electrode is coupled to a second plate within the second capacitor.

9. The memory device of claim 8 , wherein the first capacitor further includes a third plate separated from the first plate by a first dielectric material, the second capacitor further includes a fourth plate separated from the second plate by a second dielectric material, and the third plate and the fourth plate are coupled together.

10. The memory device of claim 1 , wherein the first memory cell and the second memory cell are within an interconnect structure that is above a substrate.

11. The memory device of claim 1 , wherein the shared contact electrode includes a material selected from the group consisting of titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), and an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, InOx, HfOx, AlOx, or InAlO.

12. The memory device of claim 1 , wherein the shared contact electrode is a first shared contact electrode, and the memory device further comprises:
a third memory cell including a third storage cell and a third transistor to control access to the third storage cell; and
a second shared contact electrode that is shared between the first transistor and the third transistor.

13. A memory device, comprising:
a first transistor including a first gate electrode, a first contact electrode, and a shared contact electrode, wherein the shared contact electrode is coupled to a source area or a drain area of the first transistor, and further coupled to a bit line, and the first gate electrode is coupled to a first word line;
a second transistor including a second gate electrode, a second contact electrode, and the shared contact electrode, wherein the shared contact electrode is coupled to a source area or a drain area of the second transistor, the second gate electrode is coupled to a second word line;
a channel layer shared between the first transistor and the second transistor, wherein the first gate electrode and the second gate electrode are located at a first side of the channel layer, and the first contact electrode, the shared contact electrode, and the second contact electrode are located at a second side of the channel layer opposite to the first side;
a first capacitor coupled to the first contact electrode; and
a second capacitor coupled to the second contact electrode, wherein the first transistor and the first capacitor form a first memory cell, and the second transistor and the second capacitor form a second memory cell.

14. The memory device of claim 13 , wherein the first contact electrode is coupled to the source area or the drain area of the first transistor, the second contact electrode is coupled to the source area or the drain area of the second transistor,
the first capacitor includes a first plate and a second plate separated from the first plate by a first dielectric material, the second capacitor includes a third plate and a fourth plate separated from the third plate by a second dielectric material, and the second plate and the fourth plate are coupled together.

15. The memory device of claim 13 , wherein the channel layer includes a material selected from the group consisting of CuS 2 , CuSe 2 , WSe 2 , indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly ge

Assignees

• Intel Corp

Inventors

• Alzate Vinasco Juan G
• Lajoie Travis W
• Sharma Abhishek A
• Pierce Kimberly L
• Tan Elliot N
• Chen Yu-Jin
• Le Van H
• Wang Pei-Hua
• Sell Bernhard

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title