Integrated network switch operation

Patent metadata

Field	Value
Publication number	US-11949604-B2
Application number	US-202117450097-A
Country	US
Kind code	B2
Filing date	Oct 6, 2021
Priority date	Oct 6, 2021
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

A system, method, and computer program product for implementing network state processing is provided. The method includes detecting operational states for ports of a server Internet protocol (IP) data plane component of an integrated switching device. Each operational state is analyzed and matching and action rules associated with the operational states are generated with respect to data packets arriving at the ports. Data describing each operational state is stored within a port cache structure of a port. An incoming data packet is detected at a first port and the matching and action rules are distributed between port engines of the ports. The matching and action rules are executed with respect to the incoming data packet and the incoming data packet is transmitted to a destination port. Operational functionality of the integrated switching device is enabled with respect to execution of the incoming data packet at the destination port.

First claim

What is claimed is:

1. An integrated P4 switching device comprising a processor coupled to a computer-readable memory unit, the memory unit comprising instructions that when executed by the processor implements a network state processing method comprising:
detecting, by said processor, operational states for ports of a server Internet protocol (IP) data plane component;
analyzing, by said processor, each operational state of said operational states;
generating, by said processor based on results of said analyzing, matching and action rules associated with said operational states with respect to data packets arriving at said ports;
storing, by said processor, data describing each said operational state within at least one port cache structure for at least one port of said ports;
detecting, by said processor, an incoming data packet at a first port of said ports;
distributing, by said processor, said matching and action rules between port engines of said ports and said processor;
executing, by said processor in response to said detecting and said distributing, said matching and action rules with respect to said incoming data packet;
transmitting, by said processor in response to results of said executing, said incoming data packet to a destination port of said ports;
enabling, by said processor, operational functionality of said integrated P4 switching device with respect to execution of said incoming data packet at said destination port, wherein said integrated P4 switching device comprises said ports, said at least one port cache structure, and said port engines; and
distributing, by said processor, Internet Protocol (IP) network state processing and storage (i) between said port engines and said cache structures associated with the port engines at said ports and a centralized P4/central processing unit (CPU) processing unit that utilizes external memory shared across switch ports or (ii) between a decentralized P4 based pipeline per ort, a centralized P4 pipeline, and a software based rules based processing pipeline that runs in external or embedded central processing unit (CPU) cores.

2. The integrated P4 switching device of claim 1 , wherein said distributing said matching and action rules comprises:
detecting that said matching and action rules are not located within said at least one port cache structure;
retrieving said matching and action rules from an internal memory of said processor for processing;
detecting that a buffer of said destination port is currently available; and
enabling said transmitting.

3. The integrated P4 switching device of claim 1 , wherein said distributing said matching and action rules comprises:
detecting that said matching and action rules are not located within said at least one port cache structure;
transferring said matching and action rules to an internal memory of said processor for execution;
detecting that a buffer of said destination port is currently available; and
enabling said transmitting.

4. The integrated P4 switching device of claim 1 , wherein said distributing said matching and action rules comprises:
detecting that a buffer of said destination port is currently available; and
enabling said transmitting.

5. The integrated P4 switching device of claim 1 , wherein said distributing said matching and action rules comprises:
detecting that said matching and action rules are located within said at least one port cache structure; and
enabling said transmitting.

6. The integrated P4 switching device of claim 1 , wherein said processor comprises centralized programming protocol-independent packet processor (P4) code comprising said matching and action rules.

7. The integrated P4 switching device of claim 1 , wherein said processor comprises decentralized programming protocol-independent packet processor (P4) code comprising said matching and action rules.

8. A network state processing method comprising:
detecting, by a processor of an integrated P4 switching device, operational states for ports of a server Internet protocol (IP) data plane component;
analyzing, by said processor, each operational state of said operational states;
generating, by said processor based on results of said analyzing, matching and action rules associated with said operational states with respect to data packets arriving at said ports;
storing, by said processor, data describing each said operational state within at least one port cache structure for at least one port of said ports;
detecting, by said processor, an incoming data packet at a first port of said ports;
distributing, by said processor, said matching and action rules between port engines of said ports and said processor;
executing, by said processor in response to said detecting and said distributing, said matching and action rules with respect to said incoming data packet;
transmitting, by said processor in response to results of said executing, said incoming data packet to a destination port of said ports;
enabling, by said processor, operational functionality of said integrated P4 switching device with respect to execution of said incoming data packet at said destination port, wherein said integrated P4 switching device comprises said ports, said at least one port cache structure, and said port engines; and
distributing, by said processor, Internet Protocol (IP) network state processing and storage (i) between said port engines and said cache structures associated with the port engines at said ports and a centralized P4/central processing unit (CPU) processing unit that utilizes external memory shared across switch ports or (ii) between a decentralized P4 based pipeline per ort, a centralized P4 pipeline, and a software based rules based processing pipeline that runs in external or embedded central processing unit (CPU) cores.

9. The method of claim 8 , wherein said distributing said matching and action rules comprises:
detecting that said matching and action rules are not located within said at least one port cache structure;
retrieving said matching and action rules from an internal memory of said processor for processing;
detecting that a buffer of said destination port is currently available; and
enabling said transmitting.

10. The method of claim 8 , wherein said distributing said matching and action rules comprises:
detecting that said matching and action rules are not located within said at least one port cache structure;
transferring said matching and action rules to an internal memory of said processor for execution;
detecting that a buffer of said destination port is currently available; and
enabling said transmitting.

11. The method of claim 8 , wherein said distributing said matching and action rules comprises:
detecting that a buffer of said destination port is currently available; and
enabling said transmitting.

12. The method of claim 8 , wherein said distributing said matching and action rules comprises:
detecting that said matching and action rules are located within said at least one port cache structure; and
enabling said transmitting.

13. The method of claim 8 , wherein said processor comprises centralized programming protocol-independent packet processor (P4) code comprising said matching and action rules.

14. The method of claim 8 , wherein said processor comprises decentralized programming protocol-independent packet processor (P4) code comprising said matching and action rules.

15. The method of claim 8 , further comprising:
providing at least one support service for at least one of creating, integrating, hosting, maintaining, and deploying com

Assignees

• IBM
• Inernational Business Machines Corp

Inventors

• Recio Renato J
• Gampel Eran
• Basso Claude
• Sagi Gal
• Laden Guy

Classifications

• H04L49/9026 Primary

  Single buffer per packet · CPC title

• H04L49/3027

  Output queuing · CPC title

• H04L49/109 Primary

  Integrated on microchip, e.g. switch-on-chip · CPC title

• H04L49/111

  Switch interfaces, e.g. port details · CPC title

• H04L49/15

  Interconnection of switching modules · CPC title