Pulse width modulation circuit, method for pulse width modulation, and electronic device

Patent metadata

Field	Value
Publication number	US-11949422-B2
Application number	US-202117642023-A
Country	US
Kind code	B2
Filing date	Mar 9, 2021
Priority date	Apr 14, 2020
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

A pulse width modulation (PWM) circuit, a method for PWM, and an electronic device are provided. In the PWM circuit, a control word providing circuit can generate, based on an obtained target duty cycle, two target frequency control words with a ratio of the target duty cycle, and output the two target frequency control words to a pulse generation circuit, wherein a ratio of the first target frequency control word to the second target frequency control word is the target duty cycle; and the pulse generation circuit can output a target pulse signal with the target duty cycle under the control of the two target frequency control words.

First claim

What is claimed is:

1. A pulse width modulation (PWM) circuit, wherein the PWM circuit comprises a control word providing circuit and a pulse generation circuit, and the control word providing circuit is connected to the pulse generation circuit;
the control word providing circuit is configured to: obtain a target duty cycle, generate a first target frequency control word and a second target frequency control word based on the target duty cycle, and output the first target frequency control word and the second target frequency control word to the pulse generation circuit, wherein a ratio of the first target frequency control word to the second target frequency control word is the target duty cycle;
the pulse generation circuit is configured to output, in response to the first target frequency control word and the second target frequency control word, a target pulse signal whose duty cycle is the target duty cycle;
the pulse generation circuit comprises a comparison sub-circuit, a pulse generation sub-circuit and an output selection sub-circuit;
the comparison sub-circuit is respectively connected to the control word providing circuit, the pulse generation sub-circuit and the output selection sub-circuit, the control word providing circuit is configured to output the first target frequency control word and the second target frequency control word to the comparison sub-circuit; and the comparison sub-circuit is configured to: determine whether the first target frequency control word is equal to the second target frequency control word; if the first target frequency control word is not equal to the second target frequency control word, output the first target frequency control word and the second target frequency control word to the pulse generation sub-circuit and output a first control signal to the output selection sub-circuit; and the first target frequency control word is equal to the second target frequency control word, output a second control signal to the output selection sub-circuit;
the pulse generation sub-circuit is connected to the output selection sub-circuit, and the pulse generation sub-circuit is configured to: generate the target pulse signal and output the target pulse signal to the output selection sub-circuit in response to the first target frequency control word and the second target frequency control word; and
the output selection sub-circuit is configured to: output, in response to the first control signal, the target pulse signal provided by the pulse generation sub-circuit, and output, in response to the second control signal, a target pulse signal whose duty cycle is 1.

2. The PWM circuit according to claim 1 , wherein the control word providing circuit comprises a controller and a memory, the memory stores a plurality of control word pairs, each of the control word pairs comprises a first candidate frequency control word and a second candidate frequency control word, and a ratio of the first candidate frequency control word to the second candidate frequency control word comprised in any one of the control word pairs is different from a ratio of the first candidate frequency control word to the second candidate frequency control word comprised in any other control word pair;
the controller is connected to the memory, and the controller is configured to determine, based on the target duty cycle, a target control word pair from the plurality of control word pairs stored in the memory, wherein a ratio of a first candidate frequency control word to a second candidate frequency control word comprised in the target control word pair is the target duty cycle; and
the controller is further configured to: determine the first candidate frequency control word comprised in the target control word pair as the first target frequency control word, and determine the second candidate frequency control word comprised in the target control word pair as the second target frequency control word.

3. The PWM circuit according to claim 2 , wherein the memory has a plurality of storage areas, each of the storage areas stores one control word pair, and control word pairs stored in different storage areas are different; and
the controller is configured to: determine an address of a target storage area from the plurality of storage areas based on the target duty cycle, and obtain the target control word pair from the target storage area based on the address of the target storage area, wherein
the address A of the target storage area satisfies: A=A1+D/r, A1 is a reference address, D is the target duty cycle, and r is a resolution of the target duty cycle.

4. The PWM circuit according to claim 1 , wherein the pulse generation sub-circuit comprises an initial pulse generation module and a target pulse generation module;
the initial pulse generation module is connected to the target pulse generation module, and the initial pulse generation module is configured to: generate a plurality of initial pulses and output the plurality of initial pulses to the target pulse generation module, wherein a phase difference between any two adjacent initial pulses is the same; and
the target pulse generation module is further respectively connected to the comparison sub-circuit and the output selection sub-circuit, and the target pulse generation module is configured to: generate the target pulse signal whose duty cycle is the target duty cycle based on the plurality of initial pulses, and the first target frequency control word and the second target frequency control word that are output by the comparison sub-circuit, and output the target pulse signal to the output selection sub-circuit.

5. The PWM circuit according to claim 4 , wherein the target pulse generation module comprises: an input unit, a selection unit and an output unit;
the input unit is respectively connected to the control word providing circuit and the selection unit, and the input unit is configured to output a selection control signal to the selection unit based on the first target frequency control word and the second target frequency control word;
the selection unit is further respectively connected to the initial pulse generation module and the output unit, and the selection unit is configured to: select an initial candidate pulse from the plurality of initial pulses in response to the selection control signal, and output the initial candidate pulse to the output unit; and
the output unit is further connected to the output selection sub-circuit, and the output unit is configured to: generate the target pulse signal based on the initial candidate pulse, and output the target pulse signal to the output selection sub-circuit.

6. The PWM circuit according to claim 5 , wherein the input unit comprises: a first register, a second register, a third register, a fourth register, a first adder, and a second adder; the selection unit comprises: a first selector, a second selector, and a third selector; and the output unit comprises: a D flip-flop, a first inverter, and a second inverter;
the first adder and the second adder are connected to the control word providing circuit and the third register, respectively, the first adder, the first register, the second register and the first selector are sequentially connected, the second adder, the third register, the fourth register and the second selector are sequentially connected, the second register is further connected to a first clock signal terminal, and the first register, the third register and the fourth register are further respectively connected to a second clock signal terminal;
the first adder is configured to: add the first target frequency control word and information stored in the third register, and store a summation result in the first register at a rising edge of a second clock signal provided

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Xiangye
• Xiu Liming

Classifications

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title