Nonvolatile semiconductor memory including a read operation

Patent metadata

Field	Value
Publication number	US-11948640-B2
Application number	US-202117371568-A
Country	US
Kind code	B2
Filing date	Jul 9, 2021
Priority date	Dec 3, 2008
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

First claim

What is claimed is:

1. A memory device comprising:
a first transistor;
a second transistor;
a plurality of memory cells electrically connected in series between the first transistor and the second transistor;
a source line electrically connected to the first transistor;
a hit line electrically connected to the second transistor;
a plurality of word lines electrically connected to gates of the plurality of memory cells, respectively;
a sense amplifier including
a first node,
a third transistor including a first end electrically connected to the bit line and a second end electrically connected to the first node,
a fourth transistor including a first end electrically connected to the second end of the third transistor and to the first node,
a fifth transistor including a gate electrically connected to the first node,
a sixth transistor including a first end electrically connected to a first end of the fifth transistor,
a seventh transistor including a first end electrically connected to the first end of the fifth transistor,
a first data latch electrically connected to a second end of the sixth transistor, and
a second data latch electrically connected to a second end of the seventh transistor, and

a controller configured to perform a read operation including
a first period,
a second period after the first period,
a third period after the second period,
a fourth period after the third period, and
a fifth period after the fourth period, and
at least during the second to fourth periods, a first voltage being applied to one of the plurality of word lines, and a second voltage higher than the first voltage being applied to another one of the word lines,
during the first period, a third voltage being applied to a gate of the fourth transistor to turn on the fourth transistor,
during the second period, a fourth voltage being applied to a gate of the fourth transistor to turn off the fourth transistor, and a fifth voltage being applied to a gate of the third transistor to turn on the third transistor,
after the second period, a sixth voltage being applied to a gate of the sixth transistor to turn on the sixth transistor,
during the third period, a seventh voltage being applied to the gate of the third transistor to turn off the third transistor,
during the fourth period, an eighth voltage being applied to the gate of the third transistor to turn on the third transistor, and
after the fourth period, a ninth voltage being applied to a gate of the seventh transistor to turn on the seventh transistor.

2. The memory device according to claim 1 ,
wherein the sense amplifier further includes a first capacitor including a first end connected to the first node.

3. The memory device according to claim 1 ,
wherein during the first to fifth periods, the first voltage is applied to the one of the word lines, and the second voltage is applied to the other one of the word lines.

4. The memory device according to claim 1 ,
wherein at least during the second to fourth periods, a voltage applied to the bit line is kept at a same level.

5. The memory device according to claim 4 ,
wherein at least during the second to fourth periods, the voltage applied to the bit line is kept at the same level regardless of data stored in one of the plurality of memory cells corresponding to the one of the word lines.

6. The memory device according to claim 1 , wherein
in the read operation,
the sixth voltage is applied to the gate of the sixth transistor during the third period, and
the ninth voltage is applied to the gate of the seventh transistor during the fifth period.

7. The memory device according to claim 6 , wherein
the sense amplifier further includes an eighth transistor including one end electrically connected to one end of the fifth transistor and including a gate which receives a control signal, wherein
the control signal is activated during both the third period and the fifth period.

8. The memory device according to claim 7 , wherein
each of the third transistor the fourth transistor is of a first polarity type, and
each of the fifth transistor and the eighth transistor is of a second polarity type which is opposite to the first polarity type.

9. The memory device according to claim 1 , wherein
the sense amplifier further includes a ninth transistor including a first end electrically connected to the bit line and a second end electrically connected to the first end of the third transistor, and
at least during the second to fourth periods, a clamp signal applied to a gate of the ninth transistor is kept at a same level.

10. The memory device according to claim 9 , wherein
the sense amplifier further includes a tenth transistor having a first end electrically connected the second end of the ninth transistor, a gate of the tenth transistor being electrically connected to one of the first data latch and the second data latch.

11. A method of controlling a memory device,
the memory device including:
a first transistor,
a second transistor,
a plurality of memory cells,
a source line,
a bit line,
a plurality of word lines, and
a sense amplifier, the sense amplifier including:
a first node,
a third transistor including a first end electrically connected to the bit line and a second end electrically connected to the first node,
a fourth transistor including a first end electrically connected to the second end of the third transistor and to the first node,
a fifth transistor including a gate electrically connected to the first node,
a sixth transistor including a first end electrically connected to a first end of the fifth transistor,
a seventh transistor including a first end electrically connected to the first end of the fifth transistor,
a first data latch electrically connected to a second end of the sixth transistor, and
a second data latch electrically connected to a second end of the seventh transistor,

the method comprising:
in a read operation including
a first period,
a second period after the first period,
a third period after the second period,
a fourth period after the third period, and
a fifth period after the fourth period,
applying a first voltage to one of the word lines, and applying a second voltage higher than the first voltage to another one of the word lines, at least during the second to fourth periods,
applying a third voltage to a gate of the fourth transistor to turn on the fourth transistor during the first period,
applying a fourth voltage to the gate of the fourth transistor to turn off the fourth transistor, and applying a fifth voltage to a gate of the third transistor to turn on the third transistor during the second period,
applying a sixth voltage to a gate of the sixth transistor to turn on the sixth transistor after the second period,
applying a seventh voltage to the gate of the third transistor to turn off the third transistor during the third period,
applying an eighth voltage to the gate of the third transistor to turn on the third transistor during the fourth period, and
applying a ninth voltage to a gate of the seventh transistor to turn on the seventh transistor, after the fourth period.

12. The method according to claim 11 , further comprising:
applying the first voltage to the one of the word lines and the second voltage to the other one of the word lines during the first to fifth periods.

13. The method according to claim 11 , further comprising:
applying a voltage of a same level to the bit line, at least during the second to fourth periods.

14. The method according to claim 13 , wherein
the appl

Assignees

• Kioxia Corp

Inventors

• Iwai Makoto
• Nakamura Hiroshi

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title