Flexible queue provisioning for partitioned acceleration device

Patent metadata

Field	Value
Publication number	US-11947469-B2
Application number	US-202217675897-A
Country	US
Kind code	B2
Filing date	Feb 18, 2022
Priority date	Feb 18, 2022
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

Embodiments herein describe partitioning an acceleration device based on the needs of each user application executing in a host. In one embodiment, a flexible queue provisioning method allows the acceleration device to be dynamically partitioned by pushing the configuration through a control command queue to the device by management software running in a trusted zone. The new configuration is parsed and verified by trusted firmware, which, then, creates isolated IO command queues on the acceleration device. These IO command queues can be directly mapped to a user application, VM, or other PCIe devices. In one embodiment, each IO command queue exposes only the compute resource assigned by the trusted firmware in the acceleration device.

First claim

What is claimed is:

1. An accelerator device, comprising:
a plurality of hardware resources;
a control command queue configured to receive commands from external management software;
a plurality of input/output (IO) command queues that provide interfaces for receiving commands to perform accelerator tasks issued by an external host; and
a processor unit configured to:
assign, using the commands received in the control command queue, the plurality of hardware resources into a plurality of partitions;
assign each of the plurality of IO command queues to a respective one of the plurality of partitions; and
configure the plurality of hardware resources to communicate with the plurality of IO command queues, wherein configuring the plurality of hardware resources comprises:
configuring a first hardware resource, of a first partition of the plurality of partitions, to directly access a first IO command queue assigned to the first partition; and
configuring a separate processor to convert commands, of a second IO command queue assigned to a second partition of the plurality of partitions, into instructions for a second hardware resource of the second partition.

2. The accelerator device of claim 1 , wherein at least a first one of the plurality of IO command queues is assigned to a software entity in the host, wherein the software entity in the host comprises a user application or a virtual machine.

3. The accelerator device of claim 2 , wherein at least a second one of the plurality of IO command queues is assigned to a different accelerator device via a peer-to-peer (P2P) PCIe connection.

4. The accelerator device of claim 1 , wherein hardware resources in a first partition of the plurality of partitions cannot access the IO command queues assigned to different partitions of the plurality of partitions.

5. The accelerator device of claim 4 , further comprising:
memory protection circuitry configured to, in response to the commands received from the external management software, prevent data for the plurality of partitions to be shared with hardware resources in a different partition.

6. The accelerator device of claim 1 , wherein the plurality of hardware resources form a heterogeneous processing system with different types of processing elements.

7. The accelerator device of claim 1 , wherein the processor unit is further configured to, at boot time, use the commands received from the external management software to allocate the plurality of IO command queues and establish the plurality of partitions.

8. The accelerator device of claim 7 , wherein the processor unit is further configured to, at runtime, use additional commands received from the external management software to alter the plurality of partitions and the plurality of IO command queues to form a different set of partitions.

9. The accelerator device of claim 1 , further comprising:
a plurality of virtual functions, each encapsulating a respective one of the plurality of IO command queues.

10. A system on a chip (SoC), comprising:
a plurality of hardware resources;
a control command queue configured to receive commands from external management software;
a plurality of input/output (IO) command queues that provide interfaces for receiving commands to perform accelerator tasks issued by an external host; and
a processor unit configured to:
assign, using the commands received in the control command queue, the plurality of hardware resources into a plurality of partitions;
assign each of the plurality of IO command queues to a respective one of the plurality of partitions; and
configure the plurality of hardware resources to communicate with the plurality of IO command queues, wherein configuring the plurality of hardware resources comprises:
configuring a first hardware resource, of a first partition of the plurality of partitions, to directly access a first IO command queue assigned to the first partition; and
configuring a separate processor to convert commands, of a second IO command queue assigned to a second partition of the plurality of partitions, into instructions for a second hardware resource of the second partition.

11. The SoC of claim 10 , wherein each of the plurality of IO command queues is assigned to a different software entity in the host, wherein the software entities in the host comprise user applications or virtual machines.

12. The SoC of claim 10 , wherein hardware resources in a first partition of the plurality of partitions cannot access the IO command queues assigned to different partitions of the plurality of partitions.

13. The SoC of claim 12 , further comprising:
memory protection circuitry configured to, in response to the commands received from the external management software, prevent data for the plurality of partitions to be shared with hardware resources in a different partition.

14. The SoC of claim 10 , wherein the plurality of hardware resources can form a heterogeneous processing system with different types of processing elements.

15. The SoC of claim 10 , wherein the processor unit is further configured to, at boot time, use the commands received from the external management software to allocate the plurality of IO command queues and establish the plurality of partitions.

16. The SoC of claim 15 , wherein the processor unit is further configured to, at runtime, use additional commands received from the external management software to alter the plurality of partitions and the plurality of IO command queues to form a different set of partitions.

17. The SoC of claim 10 , further comprising:
a plurality of virtual functions, each encapsulating a respective one of the plurality of IO command queues.

18. A method comprising:
advertising a control command queue in an acceleration device to external management software;
receiving, at the control command queue, commands for establishing IO command queues;
allocating the IO command queues, wherein each of the IO command queues corresponds to a respective partition of a plurality of partitions formed from hardware resources in the acceleration device, wherein allocating the IO command queues comprises:
configuring a first hardware resource, of a first partition of the plurality of partitions, to directly access a first IO command queue assigned to the first partition; and
configuring a separate processor to convert commands, of a second IO command queue assigned to a second partition of the plurality of partitions, into instructions for a second hardware resource of the second partition; and

informing designated applications executing in a host coupled to the acceleration device that the IO command queues have been allocated.

19. The method of claim 18 , further comprising:
encapsulating each of the IO command queues in a respective virtual function; and
advertising the virtual functions as new PCIe devices to the designated applications executing in the host.

20. The method of claim 18 , further comprising:
establishing memory protections in the acceleration device for the IO command queues to prevent hardware resources in one of the partitions from accessing data assigned to a different partition.

Assignees

• Xilinx Inc

Inventors

• Zhen Cheng
• Santan Sonal
• Ma Min
• Lan Chien-Wei

Classifications

• G06F13/102 Primary

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F2213/0026

  PCI express · CPC title