Display substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-11943984-B2
Application number	US-202017297838-A
Country	US
Kind code	B2
Filing date	Jul 15, 2020
Priority date	Jul 15, 2020
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A display substrate includes: a base substrate; a plurality of sub-pixels, each sub-pixel including a light-emission device including a first electrode; a plurality of signal lines including at least a first signal line and a second signal line; a signal line lead in a non-display area; and a signal line transfer structure on the base substrate, wherein the signal line transfer structure is configured to connect the signal line lead and the second signal line, the signal line transfer structure and the first signal line are located in the same layer, and the signal line transfer structure is spaced apart from the first signal line. An orthographic projection of the first electrode of at least one of the sub-pixels on the base substrate at least partially overlaps with an orthographic projection of each of the first signal line and the signal line transfer structure on the base substrate.

First claim

What is claimed is:

1. A display substrate, the display substrate comprising a display area and a non-display area, wherein the display substrate comprises:
a base substrate;
a plurality of sub-pixels in the display area, wherein the plurality of sub-pixels are arranged on the base substrate in an array in a row direction and a column direction, each sub-pixel comprises a light-emission device, and the light-emission device comprises a first electrode;
a plurality of signal lines on the base substrate, wherein the plurality of signal lines comprise at least a first signal line and a second signal line, the first signal line is configured to transmit a voltage signal, and the second signal line is configured to transmit a scan signal;
a signal line lead on the base substrate, wherein the signal line lead is located in the non-display area; and
a signal line transfer structure on the base substrate, wherein the signal line transfer structure is configured to connect the signal line lead and the second signal line,
wherein the signal line transfer structure and the first signal line are located in the same layer, and the signal line transfer structure is spaced apart from the first signal line; and
wherein an orthographic projection of the first electrode of at least one of the sub-pixels on the base substrate at least partially overlaps with an orthographic projection of the first signal line on the base substrate, and the orthographic projection of the first electrode of at least one of the sub-pixels on the base substrate at least partially overlaps with an orthographic projection of the signal line transfer structure on the base substrate.

2. The display substrate of claim 1 , wherein the plurality of sub-pixels comprise at least one array of edge sub-pixels at an edge position of the display area close to the non-display area; and
an orthographic projection of the first electrode of each edge sub-pixel in the at least one array of edge sub-pixels on the base substrate at least partially overlaps with the orthographic projection of the first signal line on the base substrate, and the orthographic projection of the first electrode of each edge sub-pixel in the at least one array of edge sub-pixels on the base substrate at least partially overlaps with the orthographic projection of the signal line transfer structure on the base substrate.

3. The display substrate of claim 2 , wherein the at least one array of edge sub-pixels comprise at least one column of edge sub-pixels, and the at least one column of edge sub-pixels are arranged in a direction that is substantially the same as an extending direction of the first signal line.

4. The display substrate of claim 2 , wherein an extending direction of the signal line transfer structure and the extending direction of the first signal line are substantially the same, and the plurality of signal line transfer structures are arranged in the direction that is substantially the same as the extending direction of the first signal line.

5. The display substrate of claim 2 , wherein an orthographic projection of the signal line transfer structure, overlapping with an edge sub-pixel in the at least one array of edge sub-pixels, on the base substrate passes through an orthographic projection of the first electrode of the edge sub-pixel on the base substrate.

6. The display substrate of claim 2 , wherein the first electrode of each edge sub-pixel in the at least one array of edge sub-pixels comprises a first edge portion close to the non-display area, and an orthographic projection of the first edge portion on the base substrate at least partially overlaps with the orthographic projection of the signal line transfer structure on the base substrate, and
in a direction perpendicular to the first signal line, the signal line transfer structure is located on a side of the first signal line close to the non-display area.

7. The display substrate of claim 6 , wherein the first electrode of each edge sub-pixel in the at least one array of edge sub-pixels comprises a second edge portion away from the non-display area, and an orthographic projection of the second edge portion on the base substrate at least partially overlaps with the orthographic projection of the first signal line on the base substrate.

8. The display substrate of claim 7 , wherein the display substrate further comprises a gate driving circuit arranged on the base substrate and located in the non-display area, the signal line lead comprises a signal output line of the gate driving circuit, the signal output line is configured to output a gate scan signal, and the second signal line comprises a scan signal line for transmitting the gate scan signal.

9. The display substrate of claim 8 , wherein the display substrate further comprises an initializing voltage signal line arranged on the base substrate and located in the non-display area, the signal output line is electrically connected to the signal line transfer structure through a plurality of third via holes, and the plurality of third via holes are arranged in a direction parallel to an extending direction of the initializing voltage signal line.

10. The display substrate of claim 9 , wherein the scan signal line is electrically connected to the signal line transfer structure through a plurality of fourth via holes, and the plurality of fourth via holes are arranged in a direction perpendicular to the extending direction of the initializing voltage signal line.

11. The display substrate of claim 10 , wherein the signal line transfer structure comprises a widened portion, orthographic projections of the plurality of third via holes and orthographic projections of the plurality of fourth via holes on the base substrate all fall within an orthographic projection of the widened portion on the base substrate; and
an orthographic projection of the first edge portion of the first electrode on the base substrate at least partially overlaps with the orthographic projection of the widened portion of the signal line transfer structure on the base substrate, or,
wherein the first signal line comprises a driving voltage line for transmitting a driving voltage, and an orthographic projection of the second edge portion of the first electrode on the base substrate at least partially overlaps with an orthographic projection of the driving voltage line on the base substrate, or,
wherein the first signal line further comprises a data line for transmitting a data signal, and the orthographic projection of the second edge portion of the first electrode on the base substrate also at least partially overlaps with an orthographic projection of the data line on the base substrate, or,
wherein the scan signal line is located in the first conductive layer, the signal output line is located in the second conductive layer, and the signal line transfer structure is located in the third conductive layer, or,
wherein the display substrate further comprises a reset control signal line on the base substrate, the reset control signal line is electrically connected to the signal line transfer structure through a plurality of fifth via holes, and the plurality of fifth via holes are arranged in a direction perpendicular to the extending direction of the initializing voltage signal line.

12. The display substrate of claim 10 , wherein the signal output line comprises a first sub-section of signal output line, a second sub-section of signal output line, and a third sub-section of signal output line that are sequentially connected, an orthographic projection of the first sub-section of signal output line on the base substrate falls within the orthographic projection of t

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Dai Jie
• Li De
• Yu Pengfei
• Shang Tinghua

Classifications

• H10K59/805

  Electrodes · CPC title

• H10K59/353 Primary

  characterised by the geometrical arrangement of the RGB subpixels · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title