Display panel including light-emitting units in through-holes of a retaining wall structure, and manufacturing method thereof

US11943949B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11943949-B2
Application numberUS-202016753840-A
CountryUS
Kind codeB2
Filing dateJan 16, 2020
Priority dateJan 7, 2020
Publication dateMar 26, 2024
Grant dateMar 26, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel includes a first substrate including a first leading line, a second substrate including a cover plate, a first electrode disposed on the cover plate in a direction of the first substrate and extending from a non-light-emitting region to light-emitting region, and a second leading line disposed on the first electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising a light-emitting region and a non-light-emitting region surrounding the light-emitting region; a first substrate, wherein a first leading line is disposed on one side of the first substrate; and a second substrate connected to the side of the first substrate comprising the leading line; wherein the second substrate comprises a cover plate; a first electrode disposed on one side of the cover plate in a direction of the first substrate, and extending from the non-light-emitting region to the light-emitting region; a retaining wall structure disposed on the first electrode, wherein the retaining wall structure comprises a plurality of through-holes and a plurality of retaining walls surrounding the through-holes, and the retaining walls are disposed in the non-light-emitting region; a light-emitting layer comprising a plurality of light-emitting units, wherein any one of the light-emitting units is correspondingly disposed in the through-holes of the retaining wall structure; a second electrode disposed on the light-emitting layer and extending to cover a portion of the retaining wall structure adjacent to the second electrode; a packaging layer disposed on the first electrode and covering the retaining wall structure, the light-emitting layer, and the second electrode; and a second leading line disposed on the first electrode of the non-light-emitting region, wherein the second leading line penetrates through the retaining wall structure and the packaging layer; wherein the first substrate comprises: a base substrate; a light-shielding metal layer disposed in the non-light-emitting region on the base substrate; a buffer layer disposed on the second substrate and covering the light-shielding metal layer; an active layer disposed on the buffer layer; a first insulating layer disposed on the active layer, wherein an orthographic projection of the first insulating layer on the base substrate completely falls within an orthographic projection of the active layer on the base substrate; a first metal layer disposed on the first insulating layer; and a second insulating layer disposed on the buffer layer and covering the active layer, the first insulating layer, and the first metal layer; wherein the active layer comprises: a first active layer disposed in the non-light-emitting region and corresponding to the light-shielding metal layer; a second active layer disposed in the light-emitting region; a second metal layer disposed on the second insulating layer and comprising a first metal segment disposed in the non-light-emitting region and corresponding to the first active layer, wherein the first metal segment comprises at least two pins, one of the pins penetrates through the second insulating layer to connect to the first active layer, and another pin penetrates through the second insulating layer and the buffer layer to connect to the light-shielding metal layer; and a third insulating layer disposed on the second insulating layer and covering the second metal layer, wherein a via hole is defined in the third insulating layer corresponding to the first metal segment, the first leading line is disposed on an inner surface of the via hole and covers a region where the first metal segment is exposed from the via hole, and the first leading line is connected to the first metal segment. 2. The display panel as claimed in claim 1 , wherein the second electrode extends from a surface of the corresponding light-emitting unit to the retaining wall structure of the non-light-emitting region, and an interval is defined between the second electrode and the second leading line which are disposed on the retaining wall structure. 3. The display panel as claimed in claim 1 , wherein the first leading line corresponds to the second leading line disposed in the non-light-emitting region. 4. The display panel as claimed in claim 1 , wherein a material of the first leading line comprises at least one of indium zinc oxide, indium tin oxide, aluminum, or silver.

Assignees

Inventors

Classifications

  • comprising light absorbing layers, e.g. black layers · CPC title

  • Encapsulations · CPC title

  • H10K50/813Primary

    characterised by their shape · CPC title

  • H10K59/127Primary

    comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates · CPC title

  • comprising light absorbing layers, e.g. light-blocking layers · CPC title

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Frequently asked questions

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What does patent US11943949B2 cover?
A display panel includes a first substrate including a first leading line, a second substrate including a cover plate, a first electrode disposed on the cover plate in a direction of the first substrate and extending from a non-light-emitting region to light-emitting region, and a second leading line disposed on the first electrode.
Who is the assignee on this patent?
Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K50/813. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 26 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).