Shingled solar cell module

Patent metadata

Field	Value
Publication number	US-11942561-B2
Application number	US-202217869513-A
Country	US
Kind code	B2
Filing date	Jul 20, 2022
Priority date	May 27, 2014
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A high efficiency configuration for a solar cell module comprises solar cells conductively bonded to each other in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency.

First claim

What is claimed is:

1. A method of manufacturing a solar cell comprising:
providing a monocrystalline silicon wafer having a front surface, a rear surface and a thickness between the front and rear surfaces;
forming trenches in the front surface of the silicon wafer, each trench having a depth, a length, a width, and walls, the depth of each trench not greater than the thickness of the silicon wafer;
depositing a first amorphous silicon layer on the front surface of the silicon wafer;
depositing a second amorphous silicon layer on the rear surface of the silicon wafer;
depositing a first transparent conductive oxide (TCO) onto the first amorphous silicon layer forming a front TCO layer and into the trenches formed in the silicon wafer such that the first TCO coats and passivates the walls of each trench;
depositing a second TCO onto the second amorphous silicon layer forming a rear TCO layer;
forming conductive grid lines on the front and rear TCO layers; and
after depositing the first TCO into the trenches, dicing the silicon wafer in line with each trench to form solar cell strips.

2. The method of claim 1 , wherein the monocrystalline silicon wafer is a n-type monocrystalline silicon wafer.

3. The method of claim 1 , wherein the first amorphous silicon layer comprises an intrinsic amorphous silicon layer and a n+doped amorphous silicon layer.

4. The method of claim 3 , wherein the intrinsic amorphous silicon layer and the n+doped amorphous silicon layer are each about 5 nm thick.

5. The method of claim 1 , wherein the second amorphous silicon layer comprises an intrinsic amorphous silicon layer and a p+doped amorphous silicon layer.

6. The method of claim 5 , wherein the intrinsic amorphous silicon layer and the p+doped amorphous silicon layer are each about 5 nm thick.

7. The method of claim 1 , wherein the n+doped amorphous silicon layer is deposited on the first intrinsic amorphous silicon layer at a temperature of about 150 C to about 200 C.

8. The method of claim 1 , wherein the front TCO layer is about 65 nm thick.

9. The method of claim 1 , wherein dicing the silicon wafer forms more than two solar cell strips.

10. The method of claim 1 , wherein dicing the silicon wafer is accomplished by mechanical cleaving.

11. The method of claim 1 , wherein the depth of each trench is about 80 microns to about 150 microns.

12. The method of claim 1 , wherein the width of each trench is about 10 microns to about 100 microns.

13. The method of claim 1 , wherein forming trenches comprises laser wafer scribing.

14. The method of claim 1 , wherein after forming the trenches and before depositing the first intrinsic layer, texture etching the silicon wafer.

15. The method of claim 14 , wherein the texture etching widens the width of at least one trench.

16. The method of claim 1 , wherein after forming the trenches and before depositing the first intrinsic layer, acid cleaning the silicon wafer.

17. The method of claim 1 , wherein the silicon wafer has a length and wherein the length of each trench is substantially the same as the length of the silicon wafer.

18. The method of claim 1 , wherein the front TCO layer functions as an antireflection coating.

19. The method of claim 1 , wherein each trench has a center line running along the length of each trench and wherein dicing the silicon wafer comprises dicing the silicon wafer substantially along the center line of each trench.

20. The method of claim 1 , wherein each solar cell strip has passivated edges.

Assignees

• Maxeon Solar Pte Ltd

Inventors

• Morad Ratson
• Almogy Gilad
• Suez Itai
• Hummel Jean
• Beckett Nathan
• Lin Yafu
• Gannon John
• Starkey Michael J
• Stuart Robert
• Lance Tamir
• Maydan Dan

Classifications

• H02J2101/24

  Photovoltaics · CPC title

• H02J4/25

  for transfer of electric power between AC and DC networks, e.g. for supplying the DC section within a load from an AC mains system · CPC title

• H10F77/937

  Busbar structures for modules · CPC title

• H10F77/219

  Arrangements for electrodes of back-contact photovoltaic cells · CPC title

• H10F77/147

  Shapes of bodies · CPC title