Quantum dot devices with overlapping gates

Patent metadata

Field	Value
Publication number	US-11942516-B2
Application number	US-202217704906-A
Country	US
Kind code	B2
Filing date	Mar 25, 2022
Priority date	Jun 26, 2018
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a quantum well stack;
a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and
a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate dielectric and the quantum well stack.

2. The quantum dot device of claim 1 , wherein the first gate dielectric has an L-shaped cross-section or a U-shaped cross-section.

3. The quantum dot device of claim 1 , wherein the first gate is at least partially between a portion of the second gate and the quantum well stack.

4. The quantum dot device of claim 1 , wherein the first gate is at least partially between a portion of the second gate metal and the quantum well stack.

5. The quantum dot device of claim 1 , wherein the first gate dielectric and the second gate dielectric have different material structures.

6. The quantum dot device of claim 1 , further comprising:
an insulator material at least partially between the first gate metal and the second gate, wherein the second gate dielectric contacts the insulator material.

7. The quantum dot device of claim 1 , wherein the quantum well stack is at least partially in a fin.

8. The quantum dot device of claim 1 , wherein the first gate and the second gate are at least partially in a trench in an insulator material above the quantum well stack.

9. The quantum dot device of claim 1 , wherein the quantum dot device is a quantum computing device, comprising:
a quantum processing device, comprising the quantum well stack, the first gate, and the second gate; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the first gate and the second gate.

10. The quantum dot device of claim 9 , further comprising:
a package substrate, wherein the quantum processing device is coupled to the package substrate.

11. A quantum dot device, comprising:
a quantum well stack;
a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric;
a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric; and
an insulator material at least partially between the first gate metal and the second gate, wherein the second gate dielectric contacts the insulator material.

12. The quantum dot device of claim 11 , wherein the first gate is at least partially between a portion of the second gate and the quantum well stack.

13. The quantum dot device of claim 11 , wherein the first gate dielectric has an L-shaped cross-section or a U-shaped cross-section.

14. The quantum dot device of claim 11 , wherein the first gate dielectric and the second gate dielectric have different material structures.

15. The quantum dot device of claim 11 , wherein the quantum well stack is at least partially in a fin.

16. The quantum dot device of claim 11 , wherein the insulator material is a first insulator material, and wherein the first gate and the second gate are at least partially in a trench in a second insulator above the quantum well stack.

17. The quantum dot device of claim 11 , wherein the quantum dot device is a quantum computing device, comprising:
a quantum processing device, comprising the quantum well stack, the first gate, the second gate, and the insulator material; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the first gate and the second gate.

18. The quantum dot device of claim 17 , further comprising:
a package substrate, wherein the quantum processing device is coupled to the package substrate.

19. A method of manufacturing a quantum dot device, the method comprising:
providing a first gate above a quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and
providing a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate dielectric and the quantum well stack.

20. The method of claim 19 , further comprising:
providing an insulator material at least partially between the first gate metal and the second gate, wherein the second gate dielectric contacts the insulator material.

Assignees

• Intel Corp

Inventors

• Thomas Nicole K
• Pillarisetty Ravi
• Singh Kanwaljit
• George Hubert C
• Michalak David J
• Lampert Lester
• Yoscovits Zachary R
• Caudillo Roman
• Roberts Jeanette M
• Clarke James S

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title