Display device including polycrystalline silicon layer, method of manufacturing polycrystalline silicon layer, and method of manufacturing display device

US11942481B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11942481-B2
Application numberUS-202117510995-A
CountryUS
Kind codeB2
Filing dateOct 26, 2021
Priority dateMar 19, 2019
Publication dateMar 26, 2024
Grant dateMar 26, 2024

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  5. First independent claim

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Abstract

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A display device may include a thin film transistor disposed on a substrate, and a display element electrically connected to the thin film transistor. The thin film transistor may include an active pattern including polycrystalline silicon, a gate insulation layer disposed on the active pattern, and a gate electrode disposed on the gate insulation layer. An average value of grain sizes of the active pattern may be in a range of about 400 nm to about 800 nm. An RMS value of a surface roughness of the active pattern may be about 4 nm or less. A method of manufacturing a polycrystalline silicon layer may include cleaning an amorphous silicon layer with hydrofluoric acid, rinsing the amorphous silicon layer with hydrogenated deionized water, and irradiating the amorphous silicon layer with a laser beam having an energy density of about 440 mJ/cm 2 to about 490 mJ/cm 2 .

First claim

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What is claimed is: 1. A method of manufacturing a polycrystalline silicon layer, comprising: forming an amorphous silicon layer on a substrate; cleaning the amorphous silicon layer with hydrofluoric acid; rinsing the amorphous silicon layer with hydrogenated deionized water; and irradiating the amorphous silicon layer with a laser beam having an energy density in a range of about 440 mJ/cm 2 to about 490 mJ/cm 2 to form the polycrystalline silicon layer. 2. The method of claim 1 , wherein a thickness of the amorphous silicon layer is in a range of about 370 Å to about 500 Å. 3. The method of claim 1 , wherein the hydrofluoric acid includes a hydrogen fluoride in an amount of about 0.5%. 4. The method of claim 1 wherein the cleaning the amorphous silicon layer is performed for a time period of about 60 seconds to about 120 seconds. 5. The method of claim 1 , wherein a hydrogen concentration of the hydrogenated deionized water is about 1.0 ppm. 6. The method of claim 1 , wherein a wavelength of the laser beam is about 308 nm. 7. The method of claim 1 , wherein a scan pitch of the laser beam is about 10 μm or less. 8. The method of claim 1 , wherein the forming the polycrystalline silicon layer includes forming grains in the polycrystalline silicon layer, an average size of the grains of the polycrystalline silicon layer is in a range of about 400 nm to about 800 nm. 9. The method of claim 1 , wherein the forming the polycrystalline silicon layer includes forming a rough surface of the polycrystalline silicon layer, a root-mean-square value of a roughness of the rough surface of the polycrystalline silicon layer is about 4 nm or less. 10. A method of manufacturing a display device, comprising: forming an amorphous silicon layer on a substrate; cleaning the amorphous silicon layer with hydrofluoric acid; rinsing the amorphous silicon layer with hydrogenated deionized water; irradiating the amorphous silicon layer with a laser beam having an energy density in a range of about 440 mJ/cm 2 to about 490 mJ/cm 2 to form a polycrystalline silicon layer; etching the polycrystalline silicon layer to form a polycrystalline silicon pattern; forming an insulation layer on the polycrystalline silicon pattern; forming a gate electrode on the insulation layer; injecting an ion at a portion of the polycrystalline silicon pattern to form an active pattern; and forming a display element on the gate electrode. 11. The method of claim 10 , wherein a scan pitch of the laser beam is about 10 μm or less. 12. The method of claim 10 , wherein the forming the display element comprises: forming a first electrode on the gate electrode, the first electrode being electrically connected to the active pattern; forming an emission layer on the first electrode; and forming a second electrode on the emission layer.

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What does patent US11942481B2 cover?
A display device may include a thin film transistor disposed on a substrate, and a display element electrically connected to the thin film transistor. The thin film transistor may include an active pattern including polycrystalline silicon, a gate insulation layer disposed on the active pattern, and a gate electrode disposed on the gate insulation layer. An average value of grain sizes of the a…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/36. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 26 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).