Maintenance operations in a DRAM

Patent metadata

Field	Value
Publication number	US-11941256-B2
Application number	US-202217829207-A
Country	US
Kind code	B2
Filing date	May 31, 2022
Priority date	Jan 22, 2009
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

First claim

What is claimed is:

1. A memory device comprising a dynamic random access memory (DRAM) chip that includes:
a plurality of memory banks, each bank including a plurality of rows of memory cells;
a command interface operable to receive a refresh command from a memory controller external to the DRAM chip;
refresh circuitry configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller; and
control logic to configure the command interface to enter a calibration mode during the refresh time interval;
wherein the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

2. The memory device of claim 1 , wherein the command interface is operable to receive a test pattern on the command interface as part of the calibration operation.

3. The memory device of claim 1 , wherein, during the calibration mode, the command interface of the DRAM chip operates in a loopback mode.

4. The memory device of claim 3 , wherein, in the loopback mode, data received by the command interface from the memory controller on a first data path is transmitted by the DRAM chip to the memory controller on a second data path.

5. The memory device of claim 4 , including loopback circuitry coupled to the command interface.

6. The memory device of claim 5 , wherein the loopback circuitry couples the second data path to the first data path when the command interface of the DRAM chip operates in the loopback mode.

7. The memory device of claim 1 , wherein the command interface is configured to perform a phase calibration operation in the calibration mode during the refresh time interval.

8. The memory device of claim 1 , wherein the command interface is configured to enter the calibration mode, in response to receiving an operation code from the memory controller, and the operation code received from the memory controller includes information that specifies an order in which memory banks of the memory device are to be refreshed.

9. The memory device of claim 1 , wherein the command interface is configured to enter the calibration mode in response to receiving an operation code from the memory controller, and the operation code received from the memory controller comprises a sub-operation code of the refresh command received from the memory controller.

10. A memory device comprising a dynamic random access memory (DRAM) chip that includes:
a plurality of memory banks, each bank including a plurality of rows of memory cells;
a command interface operable to receive a refresh command from a memory controller external to the DRAM chip;
refresh circuitry configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller; and
control logic to configure the command interface to enter a calibration mode during the refresh time interval;
wherein the command interface is configured to receive a test pattern from a memory controller in the calibration mode during the refresh time interval.

11. The memory device of claim 10 , wherein, during the calibration mode, the command interface of the DRAM chip operates in a loopback mode.

12. The memory device of claim 11 , wherein, in the loopback mode, the test pattern received by the command interface from the memory controller on a first data path is transmitted by the DRAM chip to the memory controller on a second data path.

13. The memory device of claim 12 , including loopback circuitry coupled to the command interface.

14. The memory device of claim 13 , wherein the loopback circuitry couples the second data path to the first data path when the command interface of the DRAM chip operates in the loopback mode.

15. The memory device of claim 10 , wherein the command interface is configured to perform a phase calibration operation in the calibration mode during the refresh time interval.

16. The memory device of claim 10 , wherein the command interface is configured to enter the calibration mode, in response to receiving an operation code from the memory controller, while the refresh circuitry performs the one or more refresh operations.

17. The memory device of claim 16 , wherein the operation code received from the memory controller comprises a sub-operation code of the refresh command received from the memory controller.

18. A memory device comprising a dynamic access memory (DRAM) chip that includes:
a plurality of memory banks, each bank including a plurality of rows of memory cells;
a command interface operable to receive a refresh command from a memory controller external to the DRAM chip;
refresh circuitry configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller; and
control logic to configure the command interface to enter a loopback mode during the refresh time interval;
wherein the command interface is configured to receive a test pattern from a memory controller in the loopback mode during the refresh time interval.

19. The memory device of claim 18 , including loopback circuitry coupled to the command interface, wherein the loopback circuitry, when the command interface of the memory device operates in the loopback mode, couples a second data path for transmitted data from the memory device to the memory controller to a first data path for transmitting data from the memory controller to the memory device.

20. The memory device of claim 18 , wherein the command interface is configured to perform a phase calibration operation in the loopback mode during the refresh time interval.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Palmer Robert E
• Poulton John W

Classifications

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F13/1636

  using refresh · CPC title