Tri-layer semiconductor stacks for patterning features on solar cells

Patent metadata

Field	Value
Publication number	US-11935972-B2
Application number	US-202217738984-A
Country	US
Kind code	B2
Filing date	May 6, 2022
Priority date	Apr 1, 2016
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.

First claim

What is claimed is:

1. A solar cell, comprising:
a first thin dielectric layer disposed on a back surface of a substrate;
a semiconductor structure disposed on the first thin dielectric layer such that the first thin dielectric layer is vertically between the back surface of the substrate and the semiconductor structure, wherein the semiconductor structure comprises a stack of three or more distinct semiconductor layers;
a second thin dielectric layer disposed on the back surface of the substrate;
a polycrystalline silicon emitter region disposed on the second thin dielectric layer;
a first conductive contact structure disposed on the semiconductor structure; and
a second conductive contact structure disposed on the polycrystalline silicon emitter region, wherein the polycrystalline silicon emitter region overlaps the semiconductor structure.

2. The solar cell of claim 1 , wherein the stack of the semiconductor structure is a tri-layer semiconductor stack.

3. The solar cell of claim 1 , wherein the stack of the semiconductor structure comprises:
a first semiconductor layer disposed on the first thin dielectric layer;
a P-type semiconductor layer disposed on the first semiconductor layer; and
a third semiconductor layer disposed on the P-type semiconductor layer.

4. The solar cell of claim 1 , wherein the first and second thin dielectric layer comprise silicon dioxide.

5. The solar cell of claim 1 , wherein a second portion of the back surface comprises a texturized surface.

6. The solar cell of claim 1 , wherein the polycrystalline silicon emitter region is N-type.

7. The solar cell of claim 1 , wherein the first and second conductive contact structures each comprises an aluminum-based metal seed layer disposed on the semiconductor structure and the polycrystalline silicon emitter region, respectively, and each further comprises a metal layer disposed on the aluminum-based metal seed layer.

8. The solar cell of claim 1 , further comprising:
a third thin dielectric layer disposed on a light-receiving surface of the substrate;
a polycrystalline silicon layer disposed on the third thin dielectric layer; and
an anti-reflective coating (ARC) layer disposed on the polycrystalline silicon layer.

9. A solar cell, comprising:
a first dielectric layer disposed on a back surface of a substrate;
a semiconductor stack disposed on the first dielectric layer such that the first dielectric layer is vertically between the back surface of the substrate and the semiconductor stack, wherein the semiconductor stack comprises a stack of three or more distinct semiconductor layers;
a second dielectric layer disposed on the back surface of the substrate;
a polycrystalline silicon emitter region disposed on the second dielectric layer;
a first conductive contact structure disposed on the semiconductor stack; and
a second conductive contact structure disposed on the polycrystalline silicon emitter region, wherein the polycrystalline silicon emitter region overlaps the semiconductor stack.

10. The solar cell of claim 9 , wherein the stack of the semiconductor stack is a tri-layer semiconductor stack.

11. The solar cell of claim 9 , wherein the stack of the semiconductor stack comprises:
a first semiconductor layer disposed on the first dielectric layer;
a P-type semiconductor layer disposed on the first semiconductor layer; and
a third semiconductor layer disposed on the P-type semiconductor layer.

12. The solar cell of claim 9 , wherein the first and second dielectric layer comprise silicon dioxide.

13. The solar cell of claim 9 , wherein the polycrystalline silicon emitter region is N-type.

14. The solar cell of claim 9 , wherein the first and second conductive contact structures each comprises an aluminum-based metal seed layer disposed on the semiconductor stack and the polycrystalline silicon emitter region, respectively, and each further comprises a metal layer disposed on the aluminum-based metal seed layer.

15. The solar cell of claim 9 , further comprising:
a third dielectric layer disposed on a light-receiving surface of the substrate;
a polycrystalline silicon layer disposed on the third dielectric layer; and
an anti-reflective coating (ARC) layer disposed on the polycrystalline silicon layer.

16. A solar cell, comprising:
a first thin dielectric layer disposed on a back surface of a substrate;
a first semiconductor layer disposed on the first thin dielectric layer, the first semiconductor layer comprising an outermost edge;
a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer comprising a sloped outermost edge; and
a third semiconductor layer disposed on the second semiconductor layer, the third semiconductor layer comprising a third outermost edge, wherein the third outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer;
a second thin dielectric layer disposed on the back surface of the substrate;
a polycrystalline silicon emitter region disposed on the second thin dielectric layer;
a first conductive contact structure disposed on the third semiconductor layer; and
a second conductive contact structure disposed on the polycrystalline silicon emitter region, wherein the polycrystalline silicon emitter region overlaps the first, second and third semiconductor layers.

17. The solar cell of claim 16 , wherein the second semiconductor layer comprises a P-type semiconductor layer.

18. The solar cell of claim 16 , wherein the polycrystalline silicon emitter region is N-type.

19. The solar cell of claim 16 , wherein the first and second conductive contact structures each comprises an aluminum-based metal seed layer disposed on the third semiconductor layer and polycrystalline silicon emitter region, respectively, and each further comprises a metal layer disposed on the aluminum-based metal seed layer.

20. The solar cell of claim 16 , further comprising:
a third thin dielectric layer disposed on a light-receiving surface of the substrate;
a polycrystalline silicon layer disposed on the third thin dielectric layer; and
an anti-reflective coating (ARC) layer disposed on the polycrystalline silicon layer.

Assignees

• Maxeon Solar Pte Ltd

Inventors

• Tracy Kieran Mark
• Smith David D
• Balu Venkatasubramani
• Masad Asnat
• Waldhauer Ann

Classifications

• H10F77/223

  for metallisation wrap-through [MWT] photovoltaic cells · CPC title

• H10F77/703

  of the semiconductor bodies, e.g. textured active layers · CPC title

• H10F77/211

  for photovoltaic cells · CPC title

• H10F77/147

  Shapes of bodies · CPC title

• H10F71/121

  The active layers comprising only Group IV materials · CPC title