Pseudo multi-plane read methods and apparatus for non-volatile memory devices

Patent metadata

Field	Value
Publication number	US-11935585-B2
Application number	US-202117509725-A
Country	US
Kind code	B2
Filing date	Oct 25, 2021
Priority date	Oct 25, 2021
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.

First claim

The invention claimed is:

1. An apparatus comprising:
a plurality of non-volatile memory cells arranged in a plane of a memory die, the plane comprising:
a first word line comprising a first word line portion coupled to a corresponding first group of the non-volatile memory cells;
a second word line comprising a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line; and

a control circuit configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells,
wherein the first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.

2. The apparatus of claim 1 , wherein the first word line and the second word line are each coupled to non-volatile memory cells configured to store a page of data.

3. The apparatus of claim 1 , wherein the plane further comprises a first block of the non-volatile memory cells comprising the first word line, and a second block of the non-volatile memory cells comprising the second word line, the second block different from the first block.

4. The apparatus of claim 1 , wherein the first group of the non-volatile memory cells store a first portion of a first page of data, and the second group of the non-volatile memory cells store a second portion of a second page of data.

5. The apparatus of claim 1 , wherein the first group of the non-volatile memory cells store half a page of data, and the second group of the non-volatile memory cells store half a page of data.

6. The apparatus of claim 1 , wherein the first group of the non-volatile memory cells store one quarter of a page of data, and the second group of the non-volatile memory cells store one quarter of a page of data.

7. The apparatus of claim 1 , wherein:
the plane further comprises:
a third word line comprising a third word line portion coupled to a third group of the non-volatile memory cells;
a fourth word line comprising a fourth word line portion coupled to a fourth group of the non-volatile memory cells, the fourth word line different from the third word line; and

the control circuit is further configured to apply a third voltage to the third word line portion and apply a fourth voltage to the fourth word line portion to concurrently read data from the third group of the non-volatile memory cells and the fourth group of the non-volatile memory cells,
wherein the third group of the non-volatile memory cells and the fourth group of the non-volatile memory cells each store less than a page of data.

8. The apparatus of claim 7 , wherein the third word line and the fourth word line are each coupled to non-volatile memory cells configured to store a page of data.

9. The apparatus of claim 7 , wherein the plane further comprises a first block of the non-volatile memory cells comprising the first word line, a second block of the non-volatile memory cells comprising the second word line, a third block of the non-volatile memory cells comprising the third word line, and a fourth block of the non-volatile memory cells comprising the fourth word line, wherein the first block, second block, third block and fourth block are all different blocks.

10. The apparatus of claim 7 , wherein the first group of the non-volatile memory cells store one quarter of a first page of data, the second group of the non-volatile memory cells store one quarter of a second page of data, the third group of the non-volatile memory cells store one quarter of a third page of data, and the fourth group of the non-volatile memory cells store one quarter of a fourth page of data, wherein the first page, second page, third page and fourth page are all different pages.

11. A method comprising:
receiving a first random read command and a second random read command;
determining that the first random read command requests data from a first portion of a first page of data from a first block of a plane of a memory die;
determining that the second random read command requests data from a second portion of a second page of data from a second block of the plane of the memory die, the second block different from the first block;
determining that the first portion and the second portion each comprise less than a page of data; and
concurrently reading the first portion and the second portion.

12. The method of claim 11 , wherein:
the first page of data comprises a first word line of the first block;
the second page of data comprises a second word line of the second block; and
concurrently reading comprises applying a first voltage to the first word line portion and a second voltage to the second word line portion.

13. The method of claim 11 , wherein the first portion comprises half of the first page of data, and the second portion comprises half of the second page of data.

14. The method of claim 11 , wherein concurrently reading comprises using a single sense amplifier to concurrently read the first portion and the second portion.

15. The method of claim 11 , further comprising:
receiving a third random read command and a fourth random read command;
determining that the third random read command requests data from a third portion of a third page of data from a third block of the plane of the memory die;
determining that the fourth random read command requests data from a fourth portion of a fourth page of data from a fourth block of the plane of the memory die, the third block different from the fourth block;
determining that the third portion and the fourth portion each comprise less than a page of data; and
concurrently reading the first portion, the second portion, the third portion and the fourth portion.

16. The method of claim 15 , wherein:
the third page of data comprises a third word line of the third block;
the fourth page of data comprises a fourth word line of the fourth block; and
concurrently reading further comprises applying a third voltage to the third word line portion and a fourth voltage to the fourth word line portion.

17. The method of claim 15 , wherein the first portion comprises a quarter of the first page of data, the second portion comprises a quarter of the second page of data, the third portion comprises a quarter of the third page of data, and the fourth portion comprises a quarter of the fourth page of data.

18. The method of claim 15 , wherein concurrently reading comprises using a single sense amplifier to concurrently read the first portion, the second portion, the third portion and the fourth portion.

19. An apparatus comprising:
a plurality of non-volatile memory cells arranged in a plane of a memory die, the plane comprising a first page of data in a first block and a second page of data in a second block different from the first block; and
a control circuit coupled to the plurality of non-volatile memory cells, the control circuit configured to concurrently read a first portion of the first page of data and a second portion of the second page of data,
wherein the first portion and the second portion collectively comprise a page of data.

20. The apparatus of claim 19 , wherein:
the plane further comprises a third page of data in a third block and a fourth page of data in a fourth block different from the third block; and
the control circuit is further confi

Assignees

• Sandisk Technologies Llc

Inventors

• Yang Xiang
• Ganguly Arka
• Kwon Ohwon

Classifications

• G11C11/4096 Primary

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G06F3/0613

  in relation to throughput · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title