Routing and manufacturing with a minimum area metal structure

Patent metadata

Field	Value
Publication number	US-11934764-B2
Application number	US-202117362662-A
Country	US
Kind code	B2
Filing date	Jun 29, 2021
Priority date	Jun 29, 2021
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

Manufacturing a semiconductor chip based on redefining tolerance rules to create an otherwise prohibited structure including redefining a tolerance rule to permit creation of a minimum area metal trench structure violating the tolerance rule during a routing operation; and fabricating the minimum area metal trench structure on the semiconductor substrate based on the redefined tolerance rule.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor chip based on redefining a tolerance rule to create an otherwise prohibited structure, the method comprising:
redefining a tolerance rule to permit creation of a minimum area metal trench structure violating the tolerance rule during a routing operation;
replacing an instance of the minimum area metal trench structure in a routing design file with an alternative metal trench structure based on the redefined tolerance rule; and
fabricating the alternative metal trench structure on a semiconductor substrate based on the routing design file.

2. The method of claim 1 , further comprising:
applying a nitride layer to an oxide layer of the semiconductor substrate, the oxide layer including a first metal layer and a second metal layer; and
applying a first photoresist layer to the nitride layer.

3. The method of claim 2 , further comprising:
removing a portion of the first photoresist layer from the nitride layer; and
etching a metal trench in the nitride layer where the portion of the first photoresist layer was removed.

4. The method of claim 3 , further comprising:
striping the first photoresist layer from the nitride layer;
applying a second photoresist layer to the nitride layer and the oxide layer exposed in the metal trench;
removing a section of the second photoresist layer to expose the oxide layer; and
etching the oxide layer to create a via.

5. The method of claim 4 , further comprising:
stripping the second photoresist layer from the nitride layer and the oxide layer; and
etching the metal trench in the nitride layer and the oxide layer, wherein the via is extended from the second metal layer to the first metal layer in the oxide layer; and
removing the nitride layer from the oxide layer.

6. The method of claim 5 , further comprising:
applying a conductive layer on the oxide layer and filling the via with the conductive layer; and
polishing the conductive layer from the oxide layer.

7. The method of claim 6 , further comprising applying an additional amount of the oxide layer on the conductive layer, wherein the conductive layer forms a third metal layer with the via, the via electrically connecting the third metal layer to the first metal layer in the oxide layer.

8. The method of claim 7 , wherein the third metal layer includes an upper conductive barrier, a lower conductive barrier, and side-wall conductive barriers.

9. The method of claim 1 , further comprising:
applying a photoresist layer to a second metal layer having a first via; and
removing a first section and a second section in the photoresist layer.

10. The method of claim 9 , further comprising:
cutting a first metal trench and a second metal trench in the second metal layer exposed from the first section and the second section in the photoresist layer.

11. The method of claim 10 , wherein the first metal trench and the second metal trench are filled with a conductive material.

12. The method of claim 9 , wherein the first via is self-aligned.

13. The method of claim 9 , wherein the first via is electrically connected to a first metal layer.

14. The method of claim 10 , further comprising:
applying a metal oxide on a second metal layer.

15. The method of claim 14 , further comprising:
filling the first metal trench and the second metal trench.

16. The method of claim 15 , further comprising:
removing the metal oxide from the second metal layer; and
applying an oxide layer to the second metal layer.

17. The method of claim 16 , further comprising:
applying a third metal layer to the oxide layer.

18. The method of claim 17 , wherein the third metal layer includes a second via.

19. The method of claim 18 , wherein the second via is a self-aligned via.

20. A computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising program instructions for manufacturing a semiconductor chip based on redefining a tolerance rule to create an otherwise prohibited structure that, when executed, cause a computer system to:
redefine a tolerance rule to permit creation of a minimum area metal trench structure violating the tolerance rule during a routing operation; and
replace an instance of the minimum area metal trench structure in a routing design file with an alternative metal trench structure based on the redefined tolerance rule; and
fabricate the alternative metal trench structure on a semiconductor substrate based on the routing design file.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Schultz Richard
• Yin Wenyi
• Saha Tanmoy

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title