Array substrate, preparation method therefor, and display device

Patent metadata

Field	Value
Publication number	US-11930679-B2
Application number	US-202017264283-A
Country	US
Kind code	B2
Filing date	May 12, 2020
Priority date	May 17, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.

First claim

What is claimed is:

1. An array substrate, comprising:
a substrate comprising a plurality of sub-pixel regions and a plurality of monochromatic light-emitting regions;
a thin film transistor located in each of the sub-pixel regions on the substrate, and the thin film transistor comprises a gate, an active layer, and a source-drain electrode;
a passivation layer located on a side, away from the substrate, of the thin film transistor;
a color resist located on a side, away from the substrate, of the passivation layer and located in the monochromatic light-emitting regions;
a planarization layer located on a side, away from the substrate, of the color resist and the passivation layer;
an anode located on a side, away from the substrate, of the planarization layer and electrically connected to a drain electrode in the source-drain electrode through a first through hole penetrating through the passivation layer and the planarization layer; and
dielectric layers located between the source-drain electrode and the substrate, wherein a thickness of at least one of the dielectric layers between the first through hole and the substrate is greater than a thickness of the at least one of the dielectric layers between the color resist and the substrate;
wherein the dielectric layers comprise: a buffer layer located between the substrate and the thin film transistor, and a thickness of the buffer layer between the thin film transistor and the substrate is greater than a thickness of the buffer layer between the color resist and the substrate.

2. The array substrate according to claim 1 , wherein the thickness of the buffer layer between the thin film transistor and the substrate is twice the thickness of the buffer layer between the color resist and the substrate.

3. The array substrate according to claim 1 , further comprising: a light-shielding metal layer located between the substrate and the buffer layer, and the drain electrode is electrically connected to the light-shielding metal layer through a second through hole penetrating through the buffer layer;
orthographic projections of the second through hole and the first through hole on the substrate do not overlap; and
a thickness of a part, adjacent to the second through hole, of the buffer layer is smaller than the thickness of the buffer layer between the thin film transistor and the substrate.

4. The array substrate according to claim 1 , wherein the dielectric layers further comprise: a gate insulation layer located between the gate and the active layer, and a thickness of the gate insulation layer between the first through hole and the substrate is greater than a thickness of the gate insulation layer between the color resist and the substrate.

5. The array substrate according to claim 1 , wherein the active layer in the thin film transistor is located between the gate and the substrate;
the dielectric layers further comprise: an interlayer dielectric layer located between the source-drain electrode and the gate, and the drain electrode is electrically connected to the active layer through a third through hole penetrating through the interlayer dielectric layer;
orthographic projections of the third through hole and the first through hole on the substrate do not overlap; and
a thickness of the interlayer dielectric layer between the thin film transistor and the substrate is greater than a thickness of the interlayer dielectric layer between the color resist and the substrate.

6. The array substrate according to claim 1 , wherein the substrate further comprises a plurality of white light-emitting regions; and
a thickness of the passivation layer in the white light-emitting regions is greater than a thickness of the passivation layer in the monochromatic light-emitting regions.

7. The array substrate according to claim 1 , wherein the substrate further comprises multiple white light-emitting regions; and
a thickness of at least one of the dielectric layers in the white light-emitting regions is greater than a thickness of the at least one of the dielectric layers in the monochromatic light-emitting regions.

8. The array substrate according to claim 7 , wherein a thickness of the buffer layer in the white light-emitting regions is greater than a thickness of the buffer layer in the monochromatic light-emitting regions.

9. The array substrate according to claim 7 , wherein the dielectric layers further comprise: a gate insulation layer located between the gate and the active layer, and a thickness of the gate insulation layer in the white light-emitting regions is greater than a thickness of the gate insulation layer in the monochromatic light-emitting regions.

10. The array substrate according to claim 7 , wherein the active layer in the thin film transistor is located between the gate and the substrate; and
the dielectric layers further comprise: an interlayer dielectric layer located between the source-drain electrode and the gate, and a thickness of the interlayer dielectric layer in the white light-emitting regions is greater than a thickness of the interlayer dielectric layer in the monochromatic light-emitting regions.

11. A preparation method for the array substrate according to claim 1 , comprising:
forming patterns of the gate, the active layer, and the source-drain electrode of the thin film transistor in a sub-pixel region of the substrate;
forming a pattern of the passivation layer on the thin film transistor;
forming a pattern of the color resist in the monochromatic light-emitting regions on the passivation layer;
forming a pattern of the planarization layer on the color resist and the passivation layer; and
forming a pattern of the anode on the planarization layer; wherein the anode is electrically connected to the drain electrode in the source-drain electrode through the first through hole penetrating through the passivation layer and the planarization layer; wherein
the forming the thin film transistor further comprises: forming a pattern of the dielectric layers between the source-drain electrode and the substrate, wherein the pattern of at least one of the dielectric layers formed through a half-tone mask and a once patterning process is formed in a mode that: the thickness of the at least one of the dielectric layers between the first through hole and the substrate is greater than the thickness of the at least one of the dielectric layers between the color resist and the substrate.

12. The preparation method for the array substrate according to claim 11 , wherein the forming the pattern of the dielectric layers between the source-drain electrode and the substrate comprises:
depositing an organic silicon glass solution for forming a buffer layer on the substrate and performing a pre-baking process before forming the thin film transistor;
adopting a half-tone mask to expose and develop the buffer layer subjected to the pre-baking process, wherein the pattern of the buffer layer is formed in a mode that: a thickness of a region of the buffer layer where the thin film transistor is to be formed is greater than a thickness of a region of the buffer layer where the color resist is to be formed; and
performing a post-baking process on the buffer layer to form a dense SiO x material.

13. The preparation method for the array substrate according to claim 11 , wherein the forming the pattern of the passivation layer on the thin film transistor comprises:
depositing an organic silicon glass solution for forming the passivation layer on the thin film transistor and performing a pre-baking process;
adopting a half-tone mask to expose and develop the passivation layer subjected t

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Fang Jingang
• Ding Luke
• Liu Jun
• Zhou Bin
• Cheng Jun

Classifications

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

• H10K59/38 Primary

  comprising colour filters or colour changing media [CCM] · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title