Display panel with resistance-reducing trace and signal line configured to reduce peel-off, and fabricating method thereof, and displaying device

Patent metadata

Field	Value
Publication number	US-11930677-B2
Application number	US-202117329349-A
Country	US
Kind code	B2
Filing date	May 25, 2021
Priority date	Oct 13, 2020
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A display panel and a fabricating method thereof, and a displaying device. The display panel includes a substrate, a resistance reducing trace, an inter-layer-medium layer and a signal line. The substrate is divided into a plurality of sub-pixel regions and a pixel separating region. The resistance reducing trace is provided on the pixel separating region of the substrate. The inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace. The signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.

First claim

The invention claimed is:

1. A display panel, wherein the display panel comprises:
a substrate, wherein the substrate is divided into a plurality of sub-pixel regions and a pixel separating region located between two neighboring columns of the sub-pixel regions;
a resistance reducing trace, wherein the resistance reducing trace is provided on the pixel separating region of the substrate;
an inter-layer-medium layer, wherein the inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace; and
a signal line, wherein the signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.

2. The display panel according to claim 1 , wherein in a direction perpendicular to the display panel, a difference between a thickness of the inter-layer-medium layer and a sum between a thickness of the resistance reducing trace and a thickness of the signal line is 0 to 1000 Å.

3. The display panel according to claim 1 , wherein the resistance reducing trace is distributed in the column direction along the display panel; and
in the row direction along the display panel, the width of the signal line is equal to a width of the resistance reducing trace.

4. The display panel according to claim 1 , wherein the signal line comprises a VDD signal line and/or a sensing signal line.

5. The display panel according to claim 1 , wherein the substrate located within the pixel separating region comprises a base plate and a buffer layer provided on the base plate, and the base plate is provided on one side of the buffer layer that is further away from the inter-layer-medium layer.

6. The display panel according to claim 1 , wherein the display panel further comprises:
a passivation layer, wherein the passivation layer covers the inter-layer-medium layer and the signal line;
a color-film layer, wherein the color-film layer is provided on the passivation layer; and
a flat layer, wherein the flat layer covers the color-film layer.

7. The display panel according to claim 1 , wherein the display panel further comprises a grid layer and a source-drain electrode layer that are provided in each of the sub-pixel regions; and
the resistance reducing trace and the grid layer are formed by using a same patterning process, and the signal line and the source-drain electrode layer are formed by using a same patterning process.

8. The display panel according to claim 7 , wherein the display panel further comprises a passivation layer, a color-film layer, a flat layer, and a light emitting device that is provided on the flat layer, and the light emitting device comprises an anode layer, an organic functional layer and a cathode layer that are provided in stack; and
the anode layer is provided on the flat layer, and is connected to the source-drain electrode layer via a third via hole penetrating the flat layer and the passivation layer.

9. The display panel according to claim 8 , wherein the color-film layer comprises a plurality of color-film units that are distributed in an array, and each of the color-film units comprises a plurality of color blocking units; and
the color-film layer is for performing color filtering to an emitted light ray of the light emitting device.

10. The display panel according to claim 9 , wherein the substrate comprises a base plate, a light shielding layer provided on the base plate, and a buffer layer that covers the light shielding layer and the base plate;
the display panel located within the sub-pixel regions further comprises an active layer provided on the buffer layer; and
the source-drain electrode layer is connected to the active layer via a first via hole penetrating the inter-layer-medium layer, and the source-drain electrode layer is connected to the light shielding layer via a second via hole penetrating the inter-layer-medium layer and the buffer layer.

11. The display panel according to claim 8 , wherein the display panel further comprises a packaging layer, the packaging layer comprises at least one organic packaging layer and at least one inorganic packaging layer, and the packaging layer covers the light emitting device.

12. The display panel according to claim 11 , wherein the packaging layer comprises a first inorganic packaging layer, the organic packaging layer and a second inorganic packaging layer that are provided sequentially in stack on the cathode layer.

13. A displaying device, wherein the displaying device comprises the display panel according to claim 1 .

14. A method for fabricating a display panel, wherein the method comprises:
providing a substrate, wherein the substrate is divided into a plurality of sub-pixel regions and a pixel separating region located between two neighboring columns of the sub-pixel regions;
forming a resistance reducing trace on the substrate within the pixel separating region;
forming an inter-layer-medium layer on the substrate, wherein the inter-layer-medium layer has an opening exposing the resistance reducing trace; and
forming a signal line within the opening, wherein the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.

15. The method according to claim 14 , wherein after the step of providing the substrate, the method further comprises:
forming an active layer on the substrate located within each of the sub-pixel regions;
forming a grid insulating layer on the active layer; and
forming a grid layer on the grid insulating layer, wherein the resistance reducing trace and the grid layer are formed by using a same patterning process.

16. The method according to claim 14 , wherein after the step of forming the signal line within the opening, the method further comprises:
forming a passivation layer that covers the inter-layer-medium layer and the signal line;
forming a color-film layer on the passivation layer; and
forming a flat layer covering the color-film layer.

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Huang Yongchao
• Yuan Can
• Ni Liusong
• Wang Chao
• Song Jiawen
• Luo Zhiwen
• Liu Jun
• Cheng Leilei
• Wang Qinghe
• Sun Tao

Classifications

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1315 Primary

  comprising structures specially adapted for lowering the resistance · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/38

  comprising colour filters or colour changing media [CCM] · CPC title