Digital-to-analog converter and method for digital-to-analog conversion

Patent metadata

Field	Value
Publication number	US-11929759-B2
Application number	US-202017789636-A
Country	US
Kind code	B2
Filing date	Dec 14, 2020
Priority date	Dec 30, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A DAC, for use in an iADC, is configured for converting a multi-bit word to an analog feedback signal. The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate respective analog portions based on a selection vector and a signal combiner for combining the analog portions to the analog feedback signal. In the MMS logic block switching blocks are arranged cascaded. Each switching block receives at least a portion of the multi-bit word, splits the portion into two sub-portions and forwards them to one subsequent switching block or to one output element. A weight factor is adjusted by multiplying it with the difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word is determined based on the sign of the weight accumulator.

First claim

The invention claimed is:

1. A digital-to-analog converter, DAC, for use in an incremental analog-to-digital converter, iADC, the DAC being configured for converting a multi-bit word to an analog feedback signal, the multi-bit word representing an integer within a range of integers, the DAC comprising
a mismatch shaping logic block configured to generate a selection vector with a predefined number of bits based on the multi-bit word,
a plurality of output elements configured to generate respective analog portions based on the selection vector, and
a signal combiner for combining the analog portions to the analog feedback signal,

wherein in the mismatch shaping logic block
a predetermined number of switching blocks are arranged cascaded,
each switching block is configured to receive at least a portion of the multi-bit word, to split the portion into two sub-portions and to forward each sub-portion to one further subsequent switching block or to one of the output elements, respectively,
in each switching block a weight factor is adjusted by multiplying the weight factor with the difference of the two sub-portions, and
each switching block comprises a weight accumulator provided for accumulating successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word coming to the respective switching block at a subsequent clock period within the conversion cycle of the iADC is determined based on the sign of the weight accumulator.

2. The DAC according to claim 1 , wherein in each clock period within the conversion cycle of the iADC, a new weight factor is provided, wherein successive weight factors decrease according to a monotonically decreasing function.

3. The DAC according to claim 1 , wherein each switching block further comprises
a divider configured to split the portion of the multi-bit word into two preliminary sub-portions with equal value,
a selector configured to select one of the preliminary sub-portions, the selection being based on the sign of the weight accumulator, and
an adder configured to add a remainder of the splitting conducted by the divider to the preliminary sub-portion selected by the selector.

4. The DAC according to claim 1 , wherein each switching block further comprises
a first input for receiving the portion of the multi-bit word,
a second input for providing the weight factors,
a third input for providing a clock signal, the clock signal being provided for the weight accumulator to accumulate subsequent adjusted weight factors,
a detector configured to detect, if an integer represented by the portion of the multi-bit word is even or odd,
a divider configured to split the portion of the multi-bit word into two preliminary sub-portions, the preliminary sub-portions having a smaller absolute value than the portion of the multi-bit word,
a selector configured to select one of the preliminary sub-portions, the selection being based on the sign of the weight accumulator, and
an adder configured to add a remainder of the splitting conducted by the divider to the preliminary sub-portion selected by the selector,
a first output for forwarding the first sub-portion,
a second output for forwarding the second sub-portion.

5. The DAC according to claim 4 , wherein in each switching block
the divider is configured to split the portion of the multi-bit word into two preliminary sub-portions with equal value, and
the adder is configured to add the remainder of the splitting conducted by the divider to the preliminary sub-portion selected by the selector.

6. The DAC according to claim 3 , wherein in the first switching block receiving the multi-bit word,
a further detector is configured to detect a sequence of multi-bit words representing even integers, which are larger than the minimum and smaller than the maximum integer within the range of integers, and
for each r-th multi-bit word of the detected sequence, where r is a natural number, the adder is configured to add a unit to one of the two preliminary sub-portions and a subtractor is configured to subtract the unit from the other preliminary sub-portion, wherein the selector determines the respective preliminary sub-portions based on the sign of the weight accumulator.

7. The DAC according to claim 3 , wherein in the first switching block receiving the multi-bit word,
a further detector is configured to detect multi-bit words representing even integers, which are larger than the minimum and smaller than the maximum integer within the range of integers,
a ditherer determines by random to split a multi-bit word detected by the further detector into two portions of equal or unequal value, respectively, and
in case that the ditherer determined unequal splitting, the adder is configured to add a unit to one of the two preliminary sub-portions and a subtractor is configured to subtract the unit from the other preliminary sub-portion, wherein the selector determines the respective preliminary sub-portions based on the sign of the weight accumulator.

8. The DAC according to claim 1 , the DAC further comprising a weight generator configured to provide successive weight factors for each clock period within the conversion cycle of the iADC, wherein the weight generator generates monotonically decreasing weight factors.

9. The DAC according to claim 8 , wherein the weight generator comprises
a generator input receiving a digital starting factor,
a generator output providing the weight factor,
at least one integration stage coupling the generator input to the generator output, the integration stage further comprising
a stage input to receive a digital input signal from the generator input or from a preceding integration stage, respectively,
a stage output to provide a digital output signal for a subsequent integration stage or the generator output, respectively,
a stage combiner configured to combine the digital input signal and a feedback from the digital output signal, and
a register configured to process the combination of the digital input signal and the feedback from the digital output signal, the register providing the digital output signal.

10. The DAC according to claim 8 , wherein the weight generator forwards the respective weight factor for a given clock period of the conversion cycle to each switching block.

11. An incremental analog-to-digital converter, iADC, comprising a DAC according to claim 1 , the iADC further comprising
an input for providing an analog input signal,
a combiner being configured to combine the analog input signal with the analog feedback signal from the DAC,
a loop filter being configured for filtering a combination of the analog input signal and the analog feedback signal,
an N-level quantizer for generating the multi-bit word based on an output of the loop filter,
a feedback path comprising the DAC, the DAC being configured for converting the multi-bit word from the N-level quantizer to an analog feedback signal for the combiner of the iADC, and
a decimation filter provided for filtering the multi-bit word to generate a digital system output signal.

12. An electronic device comprising the iADC according to claim 11 , the electronic device further being connected to at least one sensor, wherein the iADC is configured to perform an analog-to-digital conversion of a signal provided by the at least one sensor.

13. A digital-to-analog conversion method for converting a multi-bit word representing an integer within a range of integers to an analog feedback signal of an incremental analog-to-digital converter, iADC, the digital-to-analog conversion method comprising
generating

Assignees

• Ams Int Ag

Inventors

• Fröhlich Thomas

Classifications

• H03M1/46 Primary

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/72

  Sequential conversion in series-connected stages (H03M1/68 takes precedence) · CPC title

• H03M3/338 Primary

  by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066) · CPC title

• H03M1/0668

  the selection being based on the output of noise shaping circuits for each element · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title