Phase-locked loop reference clock management

Patent metadata

Field	Value
Publication number	US-11929751-B1
Application number	US-202218148652-A
Country	US
Kind code	B1
Filing date	Dec 30, 2022
Priority date	Dec 30, 2022
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.

First claim

What is claimed is:

1. A device, comprising:
a phase-locked loop (PLL) having a reference input;
a storage element; and
a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider, the reference clock generator coupled to the storage element, the reference clock output coupled to the reference input, and the reference clock generator configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of a first clock signal at the reference clock output remains unchanged when a frequency of a second clock signal at the interface clock input changes.

2. The device of claim 1 , wherein:
the storage element is configured to store a row value and a column value of a interface frame; and
the reference clock generator includes a mode selection circuit configured to determine that a first ratio of a product of the row and column values to a product of two and a divide ratio of the programmable clock divider is an integer.

3. The device of claim 2 , wherein the interface frame includes audio data.

4. The device of claim 2 , wherein:
the storage element is configured to store a clock scaling factor; and
upon determining that the first ratio is an integer, the reference clock generator is configured to select a divide ratio for the programmable clock divider corresponding to the clock scaling factor.

5. The device of claim 1 , wherein:
the storage element is configured to store a column number of an interface frame; and
the reference clock generator is configured to change the divide ratio for the programmable clock divider to a value of one-half the column number.

6. The device of claim 5 , wherein the device is configured to receive audio data at an audio frame rate, the audio frame rate being less than a frequency of the interface clock; and the device comprises:
a sample clock generator configured to generate a sample clock having a frequency equal to the audio frame rate; and
a sample rate detection circuit configured to determine a value indicative of the frequency of the sample clock.

7. The device of claim 6 , wherein the PLL includes a PLL frequency divider, and the device further comprises:
a ratio calculation circuit configured to determine a first ratio of the frequency of the reference clock output to the frequency of the sample clock; and
a PLL divider calculation circuit configured to determine a PLL divide ratio for PLL frequency divider based on the first ratio and the value indicative of the frequency of the sample clock.

8. A system, comprising:
a first device having a data/control output and a clock output, the first device configured to provide control information of interface frames on the data/control output and to provide a variable frequency interface clock on the clock output; and
a second device having a data/control input and a clock input, the data/control input coupled to the data/control output and the clock input coupled to the clock output, the second device having a phase-locked loop (PLL) having a PLL reference input, and the second device configured to generate a constant frequency PLL reference clock for the PLL reference input based on the variable frequency interface clock.

9. The system of claim 8 , wherein the second device comprises a programmable clock divider configured to divide the variable frequency clock by a programmable divide ratio.

10. The system of claim 9 , wherein:
the first device is configured to provide a row value and a column value of the interface frame on the data/control output; and
the second device comprises:
a storage element configured to store the row and column values; and
a reference clock generator coupled to the storage element, the reference clock generator includes a mode selection circuit configured to determine that a ratio of a product of the row and column values to a divide ratio of the programmable clock divider is an integer.

11. The system of claim 10 , wherein the mode selection circuit configured to determine that the ratio of a product of the row and column values to a product of two and the divide ratio of the programmable clock divider is an integer.

12. The system of claim 10 , wherein:
the storage element is configured to store a clock scaling factor provided by the first device; and
upon determining that the ratio is an integer, the reference clock generator is configured to select a divide ratio for the programmable clock divider corresponding to the clock scaling factor.

13. The system of claim 9 , wherein:
the second device includes a storage element configured to store a column number of the interface frame provided by the first device; and
the second device is configured to change the programmable divide ratio for the programmable clock divider to a value of one-half the column number.

14. The system of claim 13 , wherein:
the first device is configured to provide audio frames at an audio frame rate that is lower than a frequency of the variable interface clock; and
the second device includes:
a sample clock generator configured to generate a sample clock having a frequency equal to the audio frame rate; and
a sample rate detection circuit configured to determine a value indicative of the frequency of the sample clock.

15. The device of claim 14 , wherein the PLL includes a PLL frequency divider, and the second further comprises:
a ratio calculation circuit configured to determine a ratio of the frequency of the reference clock output to the frequency of the sample clock; and
a PLL divider calculation circuit configured to determine a PLL divide ratio for PLL frequency divider based on the ratio of the frequency of the reference clock output to the frequency of the sample clock and based on the value indicative of the frequency of the sample clock.

16. A method, comprising:
receiving an interface clock at a first frequency;
receiving a first value into a storage element;
determining a first divide ratio for the interface clock at the first frequency based on the first value;
dividing the interface clock's first frequency by the first divide ratio to produce a reference clock for a phase-locked loop (PLL);
receiving a second value into the storage element;
determining a second divide ratio for the interface clock at the second frequency based on the second value;
receiving the interface clock at a second frequency; and
dividing the interface clock's second frequency by the second divide ratio to produce the reference clock for the phase-locked loop (PLL), such that a frequency of the reference clock remains the same despite the change in the frequency of the interface clock.

17. The method of claim 16 , wherein:
receiving the first value comprises receiving first values that include a row value and a column value of an interface frame; and
determining the first divide ratio comprises determining that a ratio of a product of the row and column values to a product of two and a divide ratio of a clock divider is an integer.

18. The method of claim 17 , further comprising:
receiving a clock scaling factor; and
upon determining that the first divide ratio is an integer, selecting a divide ratio for the clock divider corresponding to the clock scaling factor.

19. The method of claim 16 , wherein the first value is a column value of an interface frame, and determining the first divide ratio comprises determining dividing the column value by 2.

20. The

Assignees

• Texas Instruments Inc

Inventors

• Garg Ankit
• Patki Abhijit

Classifications

• H03L7/16 Primary

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/083

  the reference signal being additionally directly applied to the generator · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/10

  for assuring initial synchronisation or for broadening the capture range · CPC title